net/mlx5: DR, Proper handling of unsupported Connect-X6DX SW steering
[ Upstream commitd421e466c2] STEs format for Connect-X5 and Connect-X6DX different. Currently, on Connext-X6DX the SW steering would break at some point when building STEs w/o giving a proper error message. Fix this by checking the STE format of the current device when initializing domain: add mlx5_ifc definitions for Connect-X6DX SW steering, read FW capability to get the current format version, and check this version when domain is being created. Fixes:26d688e33f("net/mlx5: DR, Add Steering entry (STE) utilities") Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
8f92330b08
commit
2598dd80b8
@@ -92,6 +92,7 @@ int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
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caps->eswitch_manager = MLX5_CAP_GEN(mdev, eswitch_manager);
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caps->eswitch_manager = MLX5_CAP_GEN(mdev, eswitch_manager);
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caps->gvmi = MLX5_CAP_GEN(mdev, vhca_id);
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caps->gvmi = MLX5_CAP_GEN(mdev, vhca_id);
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caps->flex_protocols = MLX5_CAP_GEN(mdev, flex_parser_protocols);
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caps->flex_protocols = MLX5_CAP_GEN(mdev, flex_parser_protocols);
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caps->sw_format_ver = MLX5_CAP_GEN(mdev, steering_format_version);
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if (mlx5dr_matcher_supp_flex_parser_icmp_v4(caps)) {
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if (mlx5dr_matcher_supp_flex_parser_icmp_v4(caps)) {
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caps->flex_parser_id_icmp_dw0 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw0);
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caps->flex_parser_id_icmp_dw0 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw0);
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@@ -223,6 +223,11 @@ static int dr_domain_caps_init(struct mlx5_core_dev *mdev,
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if (ret)
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if (ret)
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return ret;
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return ret;
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if (dmn->info.caps.sw_format_ver != MLX5_STEERING_FORMAT_CONNECTX_5) {
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mlx5dr_err(dmn, "SW steering is not supported on this device\n");
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return -EOPNOTSUPP;
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}
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ret = dr_domain_query_fdb_caps(mdev, dmn);
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ret = dr_domain_query_fdb_caps(mdev, dmn);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@@ -613,6 +613,7 @@ struct mlx5dr_cmd_caps {
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u8 max_ft_level;
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u8 max_ft_level;
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u16 roce_min_src_udp;
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u16 roce_min_src_udp;
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u8 num_esw_ports;
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u8 num_esw_ports;
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u8 sw_format_ver;
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bool eswitch_manager;
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bool eswitch_manager;
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bool rx_sw_owner;
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bool rx_sw_owner;
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bool tx_sw_owner;
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bool tx_sw_owner;
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@@ -1139,6 +1139,11 @@ enum mlx5_fc_bulk_alloc_bitmask {
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#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
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#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
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enum {
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MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
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MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
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};
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struct mlx5_ifc_cmd_hca_cap_bits {
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struct mlx5_ifc_cmd_hca_cap_bits {
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u8 reserved_at_0[0x30];
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u8 reserved_at_0[0x30];
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u8 vhca_id[0x10];
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u8 vhca_id[0x10];
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@@ -1419,7 +1424,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 general_obj_types[0x40];
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u8 general_obj_types[0x40];
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u8 reserved_at_440[0x20];
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u8 reserved_at_440[0x4];
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u8 steering_format_version[0x4];
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u8 create_qp_start_hint[0x18];
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u8 reserved_at_460[0x3];
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u8 reserved_at_460[0x3];
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u8 log_max_uctx[0x5];
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u8 log_max_uctx[0x5];
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