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clk: agilex/stratix10/n5x: fix how the bypass_reg is handled

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commit dfd1427c37 upstream.

If the bypass_reg is set, then we can return the bypass parent, however,
if there is not a bypass_reg, we need to figure what the correct parent
mux is.

The previous code never handled the parent mux if there was a
bypass_reg.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-4-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dinh Nguyen
2021-06-10 21:52:01 -05:00
committed by Greg Kroah-Hartman
parent e582a2f352
commit 308d01f525
1 changed files with 8 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/clk/socfpga/clk-periph-s10.c
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@@ -49,13 +49,18 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
{ {
struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
u32 clk_src, mask; u32 clk_src, mask;
u8 parent; u8 parent = 0;
/* handle the bypass first */
if (socfpgaclk->bypass_reg) { if (socfpgaclk->bypass_reg) {
mask = (0x1 << socfpgaclk->bypass_shift); mask = (0x1 << socfpgaclk->bypass_shift);
parent = ((readl(socfpgaclk->bypass_reg) & mask) >> parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
socfpgaclk->bypass_shift); socfpgaclk->bypass_shift);
} else { if (parent)
return parent;
}
if (socfpgaclk->hw.reg) {
clk_src = readl(socfpgaclk->hw.reg); clk_src = readl(socfpgaclk->hw.reg);
parent = (clk_src >> CLK_MGR_FREE_SHIFT) & parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
CLK_MGR_FREE_MASK; CLK_MGR_FREE_MASK;