Merge 4ac6d90867 ("Merge tag 'docs-5.15' of git://git.lwn.net/linux") into android-mainline
Steps on the way to 5.15-rc1 Fixes merge conflicts in: scripts/Makefile.lib Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I12b5165860a212fb39c98504a0729f1bab52ab54
This commit is contained in:
Greg Kroah-Hartman
@@ -58,9 +58,9 @@ source for the output is in brackets ("[]").
|
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[NR_CPUS-1]
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||||
|
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offline: CPUs that are not online because they have been
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HOTPLUGGED off (see cpu-hotplug.txt) or exceed the limit
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of CPUs allowed by the kernel configuration (kernel_max
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||||
above). [~cpu_online_mask + cpus >= NR_CPUS]
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HOTPLUGGED off or exceed the limit of CPUs allowed by the
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kernel configuration (kernel_max above).
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[~cpu_online_mask + cpus >= NR_CPUS]
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online: CPUs that are online and being scheduled [cpu_online_mask]
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@@ -96,5 +96,5 @@ online.)::
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possible: 0-127
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present: 0-3
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See cpu-hotplug.txt for the possible_cpus=NUM kernel start parameter
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as well as more information on the various cpumasks.
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See Documentation/core-api/cpu_hotplug.rst for the possible_cpus=NUM
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kernel start parameter as well as more information on the various cpumasks.
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@@ -181,10 +181,12 @@ Open cross-HT issues that core scheduling does not solve
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--------------------------------------------------------
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1. For MDS
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~~~~~~~~~~
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Core scheduling cannot protect against MDS attacks between an HT running in
|
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user mode and another running in kernel mode. Even though both HTs run tasks
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which trust each other, kernel memory is still considered untrusted. Such
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attacks are possible for any combination of sibling CPU modes (host or guest mode).
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Core scheduling cannot protect against MDS attacks between the siblings
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running in user mode and the others running in kernel mode. Even though all
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siblings run tasks which trust each other, when the kernel is executing
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code on behalf of a task, it cannot trust the code running in the
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sibling. Such attacks are possible for any combination of sibling CPU modes
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(host or guest mode).
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2. For L1TF
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~~~~~~~~~~~
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||||
|
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@@ -4202,6 +4202,15 @@
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Format: <bool> (1/Y/y=enable, 0/N/n=disable)
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default: disabled
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|
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printk.console_no_auto_verbose=
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Disable console loglevel raise on oops, panic
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or lockdep-detected issues (only if lock debug is on).
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With an exception to setups with low baudrate on
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serial console, keeping this 0 is a good choice
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in order to provide more debug information.
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Format: <bool>
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default: 0 (auto_verbose is enabled)
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printk.devkmsg={on,off,ratelimit}
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Control writing to /dev/kmsg.
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on - unlimited logging to /dev/kmsg from userspace
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|
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@@ -72,7 +72,7 @@ On PowerPC
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||||
|
||||
On other
|
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If you know of the key combos for other architectures, please
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||||
let me know so I can add them to this section.
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submit a patch to be included in this section.
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||||
|
||||
On all
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Write a character to /proc/sysrq-trigger. e.g.::
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||||
@@ -205,10 +205,12 @@ frozen (probably root) filesystem via the FIFREEZE ioctl.
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Sometimes SysRq seems to get 'stuck' after using it, what can I do?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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That happens to me, also. I've found that tapping shift, alt, and control
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on both sides of the keyboard, and hitting an invalid sysrq sequence again
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will fix the problem. (i.e., something like :kbd:`alt-sysrq-z`). Switching to
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another virtual console (:kbd:`ALT+Fn`) and then back again should also help.
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||||
When this happens, try tapping shift, alt and control on both sides of the
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keyboard, and hitting an invalid sysrq sequence again. (i.e., something like
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:kbd:`alt-sysrq-z`).
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Switching to another virtual console (:kbd:`ALT+Fn`) and then back again
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should also help.
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|
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I hit SysRq, but nothing seems to happen, what's wrong?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@@ -58,11 +58,19 @@ Kirkwood family
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||||
- Product Brief : https://web.archive.org/web/20120616201621/http://www.marvell.com/embedded-processors/kirkwood/assets/88F6180-003_ver1.pdf
|
||||
- Hardware Spec : https://web.archive.org/web/20130730091654/http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf
|
||||
- Functional Spec: https://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
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||||
- 88F6280
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||||
|
||||
- Product Brief : https://web.archive.org/web/20130730091058/http://www.marvell.com/embedded-processors/kirkwood/assets/88F6280_SoC_PB-001.pdf
|
||||
- 88F6281
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||||
|
||||
- Product Brief : https://web.archive.org/web/20120131133709/http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf
|
||||
- Hardware Spec : https://web.archive.org/web/20120620073511/http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
|
||||
- Functional Spec: https://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
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||||
- 88F6321
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||||
- 88F6322
|
||||
- 88F6323
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||||
|
||||
- Product Brief : https://web.archive.org/web/20120616201639/http://www.marvell.com/embedded-processors/kirkwood/assets/88f632x_pb.pdf
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||||
Homepage:
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https://web.archive.org/web/20160513194943/http://www.marvell.com/embedded-processors/kirkwood/
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Core:
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||||
@@ -89,6 +97,10 @@ Discovery family
|
||||
|
||||
- MV76100
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||||
|
||||
- Product Brief : https://web.archive.org/web/20140722064429/http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV76100-002_WEB.pdf
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||||
- Hardware Spec : https://web.archive.org/web/20140722064425/http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV76100_OpenSource.pdf
|
||||
- Functional Spec: https://web.archive.org/web/20111110081125/http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
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||||
|
||||
Not supported by the Linux kernel.
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||||
|
||||
Core:
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@@ -124,17 +136,23 @@ EBU Armada family
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||||
|
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Armada 38x Flavors:
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- 88F6810 Armada 380
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- 88F6811 Armada 381
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- 88F6821 Armada 382
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- 88F6W21 Armada 383
|
||||
- 88F6820 Armada 385
|
||||
- 88F6828 Armada 388
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||||
|
||||
- Product infos: https://web.archive.org/web/20181006144616/http://www.marvell.com/embedded-processors/armada-38x/
|
||||
- Functional Spec: https://web.archive.org/web/20200420191927/https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-embedded-processors-armada-38x-functional-specifications-2015-11.pdf
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||||
- Hardware Spec: https://web.archive.org/web/20180713105318/https://www.marvell.com/docs/embedded-processors/assets/marvell-embedded-processors-armada-38x-hardware-specifications-2017-03.pdf
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||||
- Design guide: https://web.archive.org/web/20180712231737/https://www.marvell.com/docs/embedded-processors/assets/marvell-embedded-processors-armada-38x-hardware-design-guide-2017-08.pdf
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||||
|
||||
Core:
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||||
ARM Cortex-A9
|
||||
|
||||
Armada 39x Flavors:
|
||||
- 88F6920 Armada 390
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||||
- 88F6925 Armada 395
|
||||
- 88F6928 Armada 398
|
||||
|
||||
- Product infos: https://web.archive.org/web/20181020222559/http://www.marvell.com/embedded-processors/armada-39x/
|
||||
|
||||
@@ -16,8 +16,6 @@ import sys
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import os
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import sphinx
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from subprocess import check_output
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# Get Sphinx version
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major, minor, patch = sphinx.version_info[:3]
|
||||
|
||||
@@ -343,6 +341,9 @@ latex_elements = {
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||||
verbatimhintsturnover=false,
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||||
''',
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||||
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||||
# For CJK One-half spacing, need to be in front of hyperref
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||||
'extrapackages': r'\usepackage{setspace}',
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||||
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||||
# Additional stuff for the LaTeX preamble.
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||||
'preamble': '''
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||||
% Prevent column squeezing of tabulary.
|
||||
@@ -355,28 +356,116 @@ latex_elements = {
|
||||
''',
|
||||
}
|
||||
|
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# At least one book (translations) may have Asian characters
|
||||
# with are only displayed if xeCJK is used
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||||
# Translations have Asian (CJK) characters which are only displayed if
|
||||
# xeCJK is used
|
||||
|
||||
cjk_cmd = check_output(['fc-list', '--format="%{family[0]}\n"']).decode('utf-8', 'ignore')
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||||
if cjk_cmd.find("Noto Sans CJK SC") >= 0:
|
||||
latex_elements['preamble'] += '''
|
||||
\\IfFontExistsTF{Noto Sans CJK SC}{
|
||||
% This is needed for translations
|
||||
\\usepackage{xeCJK}
|
||||
\\setCJKmainfont{Noto Sans CJK SC}
|
||||
\\IfFontExistsTF{Noto Serif CJK SC}{
|
||||
\\setCJKmainfont{Noto Serif CJK SC}[AutoFakeSlant]
|
||||
}{
|
||||
\\setCJKmainfont{Noto Sans CJK SC}[AutoFakeSlant]
|
||||
}
|
||||
\\setCJKsansfont{Noto Sans CJK SC}[AutoFakeSlant]
|
||||
\\setCJKmonofont{Noto Sans Mono CJK SC}[AutoFakeSlant]
|
||||
% CJK Language-specific font choices
|
||||
\\IfFontExistsTF{Noto Serif CJK SC}{
|
||||
\\newCJKfontfamily[SCmain]\\scmain{Noto Serif CJK SC}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[SCserif]\\scserif{Noto Serif CJK SC}[AutoFakeSlant]
|
||||
}{
|
||||
\\newCJKfontfamily[SCmain]\\scmain{Noto Sans CJK SC}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[SCserif]\\scserif{Noto Sans CJK SC}[AutoFakeSlant]
|
||||
}
|
||||
\\newCJKfontfamily[SCsans]\\scsans{Noto Sans CJK SC}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[SCmono]\\scmono{Noto Sans Mono CJK SC}[AutoFakeSlant]
|
||||
\\IfFontExistsTF{Noto Serif CJK TC}{
|
||||
\\newCJKfontfamily[TCmain]\\tcmain{Noto Serif CJK TC}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[TCserif]\\tcserif{Noto Serif CJK TC}[AutoFakeSlant]
|
||||
}{
|
||||
\\newCJKfontfamily[TCmain]\\tcmain{Noto Sans CJK TC}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[TCserif]\\tcserif{Noto Sans CJK TC}[AutoFakeSlant]
|
||||
}
|
||||
\\newCJKfontfamily[TCsans]\\tcsans{Noto Sans CJK TC}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[TCmono]\\tcmono{Noto Sans Mono CJK TC}[AutoFakeSlant]
|
||||
\\IfFontExistsTF{Noto Serif CJK KR}{
|
||||
\\newCJKfontfamily[KRmain]\\krmain{Noto Serif CJK KR}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[KRserif]\\krserif{Noto Serif CJK KR}[AutoFakeSlant]
|
||||
}{
|
||||
\\newCJKfontfamily[KRmain]\\krmain{Noto Sans CJK KR}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[KRserif]\\krserif{Noto Sans CJK KR}[AutoFakeSlant]
|
||||
}
|
||||
\\newCJKfontfamily[KRsans]\\krsans{Noto Sans CJK KR}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[KRmono]\\krmono{Noto Sans Mono CJK KR}[AutoFakeSlant]
|
||||
\\IfFontExistsTF{Noto Serif CJK JP}{
|
||||
\\newCJKfontfamily[JPmain]\\jpmain{Noto Serif CJK JP}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[JPserif]\\jpserif{Noto Serif CJK JP}[AutoFakeSlant]
|
||||
}{
|
||||
\\newCJKfontfamily[JPmain]\\jpmain{Noto Sans CJK JP}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[JPserif]\\jpserif{Noto Sans CJK JP}[AutoFakeSlant]
|
||||
}
|
||||
\\newCJKfontfamily[JPsans]\\jpsans{Noto Sans CJK JP}[AutoFakeSlant]
|
||||
\\newCJKfontfamily[JPmono]\\jpmono{Noto Sans Mono CJK JP}[AutoFakeSlant]
|
||||
% Dummy commands for Sphinx < 2.3 (no 'extrapackages' support)
|
||||
\\providecommand{\\onehalfspacing}{}
|
||||
\\providecommand{\\singlespacing}{}
|
||||
% Define custom macros to on/off CJK
|
||||
\\newcommand{\\kerneldocCJKon}{\\makexeCJKactive}
|
||||
\\newcommand{\\kerneldocCJKoff}{\\makexeCJKinactive}
|
||||
% To customize \sphinxtableofcontents
|
||||
\\newcommand{\\kerneldocCJKon}{\\makexeCJKactive\\onehalfspacing}
|
||||
\\newcommand{\\kerneldocCJKoff}{\\makexeCJKinactive\\singlespacing}
|
||||
\\newcommand{\\kerneldocBeginSC}{%
|
||||
\\begingroup%
|
||||
\\scmain%
|
||||
}
|
||||
\\newcommand{\\kerneldocEndSC}{\\endgroup}
|
||||
\\newcommand{\\kerneldocBeginTC}{%
|
||||
\\begingroup%
|
||||
\\tcmain%
|
||||
\\renewcommand{\\CJKrmdefault}{TCserif}%
|
||||
\\renewcommand{\\CJKsfdefault}{TCsans}%
|
||||
\\renewcommand{\\CJKttdefault}{TCmono}%
|
||||
}
|
||||
\\newcommand{\\kerneldocEndTC}{\\endgroup}
|
||||
\\newcommand{\\kerneldocBeginKR}{%
|
||||
\\begingroup%
|
||||
\\xeCJKDeclareCharClass{HalfLeft}{`“,`‘}%
|
||||
\\xeCJKDeclareCharClass{HalfRight}{`”,`’}%
|
||||
\\krmain%
|
||||
\\renewcommand{\\CJKrmdefault}{KRserif}%
|
||||
\\renewcommand{\\CJKsfdefault}{KRsans}%
|
||||
\\renewcommand{\\CJKttdefault}{KRmono}%
|
||||
\\xeCJKsetup{CJKspace = true} % For inter-phrase space
|
||||
}
|
||||
\\newcommand{\\kerneldocEndKR}{\\endgroup}
|
||||
\\newcommand{\\kerneldocBeginJP}{%
|
||||
\\begingroup%
|
||||
\\xeCJKDeclareCharClass{HalfLeft}{`“,`‘}%
|
||||
\\xeCJKDeclareCharClass{HalfRight}{`”,`’}%
|
||||
\\jpmain%
|
||||
\\renewcommand{\\CJKrmdefault}{JPserif}%
|
||||
\\renewcommand{\\CJKsfdefault}{JPsans}%
|
||||
\\renewcommand{\\CJKttdefault}{JPmono}%
|
||||
}
|
||||
\\newcommand{\\kerneldocEndJP}{\\endgroup}
|
||||
% Single spacing in literal blocks
|
||||
\\fvset{baselinestretch=1}
|
||||
% To customize \\sphinxtableofcontents
|
||||
\\usepackage{etoolbox}
|
||||
% Inactivate CJK after tableofcontents
|
||||
\\apptocmd{\\sphinxtableofcontents}{\\kerneldocCJKoff}{}{}
|
||||
'''
|
||||
else:
|
||||
latex_elements['preamble'] += '''
|
||||
}{ % No CJK font found
|
||||
% Custom macros to on/off CJK (Dummy)
|
||||
\\newcommand{\\kerneldocCJKon}{}
|
||||
\\newcommand{\\kerneldocCJKoff}{}
|
||||
\\newcommand{\\kerneldocBeginSC}{}
|
||||
\\newcommand{\\kerneldocEndSC}{}
|
||||
\\newcommand{\\kerneldocBeginTC}{}
|
||||
\\newcommand{\\kerneldocEndTC}{}
|
||||
\\newcommand{\\kerneldocBeginKR}{}
|
||||
\\newcommand{\\kerneldocEndKR}{}
|
||||
\\newcommand{\\kerneldocBeginSC}{}
|
||||
\\newcommand{\\kerneldocEndKR}{}
|
||||
}
|
||||
'''
|
||||
|
||||
# Fix reference escape troubles with Sphinx 1.4.x
|
||||
|
||||
@@ -91,9 +91,10 @@ Never use anything other than ``cpumask_t`` to represent bitmap of CPUs.
|
||||
|
||||
Using CPU hotplug
|
||||
=================
|
||||
|
||||
The kernel option *CONFIG_HOTPLUG_CPU* needs to be enabled. It is currently
|
||||
available on multiple architectures including ARM, MIPS, PowerPC and X86. The
|
||||
configuration is done via the sysfs interface: ::
|
||||
configuration is done via the sysfs interface::
|
||||
|
||||
$ ls -lh /sys/devices/system/cpu
|
||||
total 0
|
||||
@@ -113,14 +114,14 @@ configuration is done via the sysfs interface: ::
|
||||
|
||||
The files *offline*, *online*, *possible*, *present* represent the CPU masks.
|
||||
Each CPU folder contains an *online* file which controls the logical on (1) and
|
||||
off (0) state. To logically shutdown CPU4: ::
|
||||
off (0) state. To logically shutdown CPU4::
|
||||
|
||||
$ echo 0 > /sys/devices/system/cpu/cpu4/online
|
||||
smpboot: CPU 4 is now offline
|
||||
|
||||
Once the CPU is shutdown, it will be removed from */proc/interrupts*,
|
||||
*/proc/cpuinfo* and should also not be shown visible by the *top* command. To
|
||||
bring CPU4 back online: ::
|
||||
bring CPU4 back online::
|
||||
|
||||
$ echo 1 > /sys/devices/system/cpu/cpu4/online
|
||||
smpboot: Booting Node 0 Processor 4 APIC 0x1
|
||||
@@ -142,6 +143,7 @@ The CPU hotplug coordination
|
||||
|
||||
The offline case
|
||||
----------------
|
||||
|
||||
Once a CPU has been logically shutdown the teardown callbacks of registered
|
||||
hotplug states will be invoked, starting with ``CPUHP_ONLINE`` and terminating
|
||||
at state ``CPUHP_OFFLINE``. This includes:
|
||||
@@ -158,9 +160,10 @@ at state ``CPUHP_OFFLINE``. This includes:
|
||||
|
||||
Using the hotplug API
|
||||
---------------------
|
||||
|
||||
It is possible to receive notifications once a CPU is offline or onlined. This
|
||||
might be important to certain drivers which need to perform some kind of setup
|
||||
or clean up functions based on the number of available CPUs: ::
|
||||
or clean up functions based on the number of available CPUs::
|
||||
|
||||
#include <linux/cpuhotplug.h>
|
||||
|
||||
@@ -186,9 +189,10 @@ During the removal of a hotplug state the teardown callback will be invoked.
|
||||
|
||||
Multiple instances
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
If a driver has multiple instances and each instance needs to perform the
|
||||
callback independently then it is likely that a ''multi-state'' should be used.
|
||||
First a multi-state state needs to be registered: ::
|
||||
First a multi-state state needs to be registered::
|
||||
|
||||
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "X/Y:online,
|
||||
Y_online, Y_prepare_down);
|
||||
@@ -197,7 +201,7 @@ First a multi-state state needs to be registered: ::
|
||||
The ``cpuhp_setup_state_multi()`` behaves similar to ``cpuhp_setup_state()``
|
||||
except it prepares the callbacks for a multi state and does not invoke
|
||||
the callbacks. This is a one time setup.
|
||||
Once a new instance is allocated, you need to register this new instance: ::
|
||||
Once a new instance is allocated, you need to register this new instance::
|
||||
|
||||
ret = cpuhp_state_add_instance(Y_hp_online, &d->node);
|
||||
|
||||
@@ -206,7 +210,8 @@ This function will add this instance to your previously allocated
|
||||
(*Y_online*) on all online CPUs. The *node* element is a ``struct
|
||||
hlist_node`` member of your per-instance data structure.
|
||||
|
||||
On removal of the instance: ::
|
||||
On removal of the instance::
|
||||
|
||||
cpuhp_state_remove_instance(Y_hp_online, &d->node)
|
||||
|
||||
should be invoked which will invoke the teardown callback on all online
|
||||
@@ -214,6 +219,7 @@ CPUs.
|
||||
|
||||
Manual setup
|
||||
~~~~~~~~~~~~
|
||||
|
||||
Usually it is handy to invoke setup and teardown callbacks on registration or
|
||||
removal of a state because usually the operation needs to performed once a CPU
|
||||
goes online (offline) and during initial setup (shutdown) of the driver. However
|
||||
@@ -226,6 +232,7 @@ hotplug operations.
|
||||
|
||||
The ordering of the events
|
||||
--------------------------
|
||||
|
||||
The hotplug states are defined in ``include/linux/cpuhotplug.h``:
|
||||
|
||||
* The states *CPUHP_OFFLINE* … *CPUHP_AP_OFFLINE* are invoked before the
|
||||
@@ -248,13 +255,14 @@ another hotplug event.
|
||||
|
||||
Testing of hotplug states
|
||||
=========================
|
||||
|
||||
One way to verify whether a custom state is working as expected or not is to
|
||||
shutdown a CPU and then put it online again. It is also possible to put the CPU
|
||||
to certain state (for instance *CPUHP_AP_ONLINE*) and then go back to
|
||||
*CPUHP_ONLINE*. This would simulate an error one state after *CPUHP_AP_ONLINE*
|
||||
which would lead to rollback to the online state.
|
||||
|
||||
All registered states are enumerated in ``/sys/devices/system/cpu/hotplug/states``: ::
|
||||
All registered states are enumerated in ``/sys/devices/system/cpu/hotplug/states`` ::
|
||||
|
||||
$ tail /sys/devices/system/cpu/hotplug/states
|
||||
138: mm/vmscan:online
|
||||
@@ -268,7 +276,7 @@ All registered states are enumerated in ``/sys/devices/system/cpu/hotplug/states
|
||||
168: sched:active
|
||||
169: online
|
||||
|
||||
To rollback CPU4 to ``lib/percpu_cnt:online`` and back online just issue: ::
|
||||
To rollback CPU4 to ``lib/percpu_cnt:online`` and back online just issue::
|
||||
|
||||
$ cat /sys/devices/system/cpu/cpu4/hotplug/state
|
||||
169
|
||||
@@ -276,14 +284,14 @@ To rollback CPU4 to ``lib/percpu_cnt:online`` and back online just issue: ::
|
||||
$ cat /sys/devices/system/cpu/cpu4/hotplug/state
|
||||
140
|
||||
|
||||
It is important to note that the teardown callbac of state 140 have been
|
||||
invoked. And now get back online: ::
|
||||
It is important to note that the teardown callback of state 140 have been
|
||||
invoked. And now get back online::
|
||||
|
||||
$ echo 169 > /sys/devices/system/cpu/cpu4/hotplug/target
|
||||
$ cat /sys/devices/system/cpu/cpu4/hotplug/state
|
||||
169
|
||||
|
||||
With trace events enabled, the individual steps are visible, too: ::
|
||||
With trace events enabled, the individual steps are visible, too::
|
||||
|
||||
# TASK-PID CPU# TIMESTAMP FUNCTION
|
||||
# | | | | |
|
||||
@@ -318,6 +326,7 @@ trace.
|
||||
|
||||
Architecture's requirements
|
||||
===========================
|
||||
|
||||
The following functions and configurations are required:
|
||||
|
||||
``CONFIG_HOTPLUG_CPU``
|
||||
@@ -339,11 +348,12 @@ The following functions and configurations are required:
|
||||
|
||||
User Space Notification
|
||||
=======================
|
||||
After CPU successfully onlined or offline udev events are sent. A udev rule like: ::
|
||||
|
||||
After CPU successfully onlined or offline udev events are sent. A udev rule like::
|
||||
|
||||
SUBSYSTEM=="cpu", DRIVERS=="processor", DEVPATH=="/devices/system/cpu/*", RUN+="the_hotplug_receiver.sh"
|
||||
|
||||
will receive all events. A script like: ::
|
||||
will receive all events. A script like::
|
||||
|
||||
#!/bin/sh
|
||||
|
||||
|
||||
@@ -107,9 +107,6 @@ also ``CONFIG_DYNAMIC_DEBUG`` in the case of pr_debug()) is defined.
|
||||
Function reference
|
||||
==================
|
||||
|
||||
.. kernel-doc:: kernel/printk/printk.c
|
||||
:functions: printk
|
||||
|
||||
.. kernel-doc:: include/linux/printk.h
|
||||
:functions: pr_emerg pr_alert pr_crit pr_err pr_warn pr_notice pr_info
|
||||
:functions: printk pr_emerg pr_alert pr_crit pr_err pr_warn pr_notice pr_info
|
||||
pr_fmt pr_debug pr_devel pr_cont
|
||||
|
||||
@@ -130,6 +130,7 @@ printed after the symbol name with an extra ``b`` appended to the end of the
|
||||
specifier.
|
||||
|
||||
::
|
||||
|
||||
%pS versatile_init+0x0/0x110 [module_name]
|
||||
%pSb versatile_init+0x0/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
|
||||
%pSRb versatile_init+0x9/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
|
||||
|
||||
@@ -28,7 +28,7 @@ find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
|
||||
|
||||
quiet_cmd_yamllint = LINT $(src)
|
||||
cmd_yamllint = ($(find_cmd) | \
|
||||
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint) || true
|
||||
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
|
||||
|
||||
quiet_cmd_chk_bindings = CHKDT $@
|
||||
cmd_chk_bindings = ($(find_cmd) | \
|
||||
|
||||
@@ -145,6 +145,11 @@ properties:
|
||||
- const: atmel,sama5d4
|
||||
- const: atmel,sama5
|
||||
|
||||
- items:
|
||||
- const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
|
||||
- const: microchip,sama7g5
|
||||
- const: microchip,sama7
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,sams70j19
|
||||
|
||||
@@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties:
|
||||
"atmel,at91sam9260-sdramc",
|
||||
"atmel,at91sam9g45-ddramc",
|
||||
"atmel,sama5d3-ddramc",
|
||||
"microchip,sam9x60-ddramc"
|
||||
"microchip,sam9x60-ddramc",
|
||||
"microchip,sama7g5-uddrc"
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
Examples:
|
||||
@@ -55,6 +56,17 @@ Examples:
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
RAMC PHY Controller required properties:
|
||||
- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
Example:
|
||||
|
||||
ddr3phy: ddr3phy@e3804000 {
|
||||
compatible = "microchip,sama7g5-ddr3phy", "syscon";
|
||||
reg = <0xe3804000 0x1000>;
|
||||
};
|
||||
|
||||
SHDWC Shutdown Controller
|
||||
|
||||
required properties:
|
||||
|
||||
@@ -221,9 +221,13 @@ properties:
|
||||
- prt,prti6q # Protonic PRTI6Q board
|
||||
- prt,prtwd2 # Protonic WD2 board
|
||||
- rex,imx6q-rex-pro # Rex Pro i.MX6 Quad Board
|
||||
- skov,imx6q-skov-revc-lt2 # SKOV IMX6 CPU QuadCore lt2
|
||||
- skov,imx6q-skov-revc-lt6 # SKOV IMX6 CPU QuadCore lt6
|
||||
- skov,imx6q-skov-reve-mi1010ait-1cp1 # SKOV IMX6 CPU QuadCore mi1010ait-1cp1
|
||||
- solidrun,cubox-i/q # SolidRun Cubox-i Dual/Quad
|
||||
- solidrun,hummingboard/q
|
||||
- solidrun,hummingboard2/q
|
||||
- solidrun,solidsense/q # SolidRun SolidSense Dual/Quad
|
||||
- tbs,imx6q-tbs2910 # TBS2910 Matrix ARM mini PC
|
||||
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
|
||||
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
|
||||
@@ -377,9 +381,12 @@ properties:
|
||||
- prt,prtvt7 # Protonic VT7 board
|
||||
- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
|
||||
- riot,imx6s-riotboard # RIoTboard i.MX6S
|
||||
- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2
|
||||
- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6
|
||||
- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
|
||||
- solidrun,hummingboard/dl
|
||||
- solidrun,hummingboard2/dl # SolidRun HummingBoard2 Solo/DualLite
|
||||
- solidrun,solidsense/dl # SolidRun SolidSense Solo/DualLite
|
||||
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
|
||||
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
|
||||
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
|
||||
@@ -418,6 +425,12 @@ properties:
|
||||
- const: dfi,fs700e-m60
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL DHCOM PicoITX Board
|
||||
items:
|
||||
- const: dh,imx6dl-dhcom-picoitx
|
||||
- const: dh,imx6dl-dhcom-som
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL Gateworks Ventana Boards
|
||||
items:
|
||||
- enum:
|
||||
@@ -469,6 +482,12 @@ properties:
|
||||
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6S DHCOM DRC02 Board
|
||||
items:
|
||||
- const: dh,imx6s-dhcom-drc02
|
||||
- const: dh,imx6s-dhcom-som
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6SL based Boards
|
||||
items:
|
||||
- enum:
|
||||
@@ -698,6 +717,7 @@ properties:
|
||||
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
|
||||
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
|
||||
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
|
||||
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
|
||||
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
|
||||
- const: fsl,imx8mm
|
||||
@@ -728,6 +748,7 @@ properties:
|
||||
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
|
||||
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: Variscite VAR-SOM-MX8MN based boards
|
||||
@@ -752,10 +773,12 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
|
||||
- boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM
|
||||
- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
|
||||
- fsl,imx8mq-evk # i.MX8MQ EVK Board
|
||||
- google,imx8mq-phanbell # Google Coral Edge TPU
|
||||
- kontron,pitx-imx8m # Kontron pITX-imx8m Board
|
||||
- mntre,reform2 # MNT Reform2 Laptop
|
||||
- purism,librem5-devkit # Purism Librem5 devkit
|
||||
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
|
||||
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
|
||||
@@ -973,6 +996,12 @@ properties:
|
||||
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
|
||||
- const: fsl,s32v234
|
||||
|
||||
- description: Traverse LS1088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- traverse,ten64 # Ten64 Networking Appliance / Board
|
||||
- const: fsl,ls1088a
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@@ -1,108 +0,0 @@
|
||||
Cortina systems Gemini platforms
|
||||
|
||||
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
|
||||
produced by Storlink Semiconductor around 2005. The company was renamed
|
||||
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
|
||||
It was derived from earlier products from Storm named SL3316 (Centroid) and
|
||||
SL3512 (Bulverde).
|
||||
|
||||
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
|
||||
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
|
||||
in turn acquired by Inphi, who seem to have discontinued this product family.
|
||||
|
||||
Many of the IP blocks used in the SoC comes from Faraday Technology.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "cortina,gemini";
|
||||
|
||||
Required nodes:
|
||||
|
||||
- soc: the SoC should be represented by a simple bus encompassing all the
|
||||
onchip devices, this is referred to as the soc bus node.
|
||||
|
||||
- syscon: the soc bus node must have a system controller node pointing to the
|
||||
global control registers, with the compatible string
|
||||
"cortina,gemini-syscon", "syscon";
|
||||
|
||||
Required properties on the syscon:
|
||||
- reg: syscon register location and size.
|
||||
- #clock-cells: should be set to <1> - the system controller is also a
|
||||
clock provider.
|
||||
- #reset-cells: should be set to <1> - the system controller is also a
|
||||
reset line provider.
|
||||
|
||||
The clock sources have shorthand defines in the include file:
|
||||
<dt-bindings/clock/cortina,gemini-clock.h>
|
||||
|
||||
The reset lines have shorthand defines in the include file:
|
||||
<dt-bindings/reset/cortina,gemini-reset.h>
|
||||
|
||||
- timer: the soc bus node must have a timer node pointing to the SoC timer
|
||||
block, with the compatible string "cortina,gemini-timer"
|
||||
See: clocksource/cortina,gemini-timer.txt
|
||||
|
||||
- interrupt-controller: the sob bus node must have an interrupt controller
|
||||
node pointing to the SoC interrupt controller block, with the compatible
|
||||
string "cortina,gemini-interrupt-controller"
|
||||
See interrupt-controller/cortina,gemini-interrupt-controller.txt
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
model = "Foo Gemini Machine";
|
||||
compatible = "cortina,gemini";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intcon>;
|
||||
|
||||
syscon: syscon@40000000 {
|
||||
compatible = "cortina,gemini-syscon", "syscon";
|
||||
reg = <0x40000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@42000000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x42000000 0x100>;
|
||||
resets = <&syscon GEMINI_RESET_UART>;
|
||||
clocks = <&syscon GEMINI_CLK_UART>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
timer@43000000 {
|
||||
compatible = "cortina,gemini-timer";
|
||||
reg = <0x43000000 0x1000>;
|
||||
interrupt-parent = <&intcon>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
|
||||
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
|
||||
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
|
||||
resets = <&syscon GEMINI_RESET_TIMER>;
|
||||
/* APB clock or RTC clock */
|
||||
clocks = <&syscon GEMINI_CLK_APB>,
|
||||
<&syscon GEMINI_CLK_RTC>;
|
||||
clock-names = "PCLK", "EXTCLK";
|
||||
syscon = <&syscon>;
|
||||
};
|
||||
|
||||
intcon: interrupt-controller@48000000 {
|
||||
compatible = "cortina,gemini-interrupt-controller";
|
||||
reg = <0x48000000 0x1000>;
|
||||
resets = <&syscon GEMINI_RESET_INTCON0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
95
Documentation/devicetree/bindings/arm/gemini.yaml
Normal file
95
Documentation/devicetree/bindings/arm/gemini.yaml
Normal file
@@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/gemini.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cortina systems Gemini platforms
|
||||
|
||||
description: |
|
||||
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
|
||||
produced by Storlink Semiconductor around 2005. The company was renamed
|
||||
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
|
||||
It was derived from earlier products from Storm named SL3316 (Centroid) and
|
||||
SL3512 (Bulverde).
|
||||
|
||||
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
|
||||
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
|
||||
in turn acquired by Inphi, who seem to have discontinued this product family.
|
||||
|
||||
Many of the IP blocks used in the SoC comes from Faraday Technology.
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: Storlink Semiconductor Gemini324 EV-Board also known
|
||||
as Storm Semiconductor SL93512R_BRD
|
||||
items:
|
||||
- const: storlink,gemini324
|
||||
- const: storm,sl93512r
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: D-Link DIR-685 Xtreme N Storage Router
|
||||
items:
|
||||
- const: dlink,dir-685
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: D-Link DNS-313 1-Bay Network Storage Enclosure
|
||||
items:
|
||||
- const: dlink,dns-313
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: Edimax NS-2502
|
||||
items:
|
||||
- const: edimax,ns-2502
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: ITian Square One SQ201
|
||||
items:
|
||||
- const: itian,sq201
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: Raidsonic NAS IB-4220-B
|
||||
items:
|
||||
- const: raidsonic,ib-4220-b
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: SSI 1328
|
||||
items:
|
||||
- const: ssi,1328
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: Teltonika RUT1xx Mobile Router
|
||||
items:
|
||||
- const: teltonika,rut1xx
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: Wiligear Wiliboard WBD-111
|
||||
items:
|
||||
- const: wiligear,wiliboard-wbd111
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: Wiligear Wiliboard WBD-222
|
||||
items:
|
||||
- const: wiligear,wiliboard-wbd222
|
||||
- const: cortina,gemini
|
||||
|
||||
- description: Wiligear Wiliboard WBD-111 - old incorrect binding
|
||||
items:
|
||||
- const: wiliboard,wbd111
|
||||
- const: cortina,gemini
|
||||
deprecated: true
|
||||
|
||||
- description: Wiligear Wiliboard WBD-222 - old incorrect binding
|
||||
items:
|
||||
- const: wiliboard,wbd222
|
||||
- const: cortina,gemini
|
||||
deprecated: true
|
||||
|
||||
additionalProperties: true
|
||||
@@ -1,31 +0,0 @@
|
||||
Mediatek mmsys controller
|
||||
============================
|
||||
|
||||
The Mediatek mmsys system controller provides clock control, routing control,
|
||||
and miscellaneous control in mmsys partition.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt2712-mmsys", "syscon"
|
||||
- "mediatek,mt6765-mmsys", "syscon"
|
||||
- "mediatek,mt6779-mmsys", "syscon"
|
||||
- "mediatek,mt6797-mmsys", "syscon"
|
||||
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt8167-mmsys", "syscon"
|
||||
- "mediatek,mt8173-mmsys", "syscon"
|
||||
- "mediatek,mt8183-mmsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
For the clock control, the mmsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek mmsys controller
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
description:
|
||||
The MediaTek mmsys system controller provides clock control, routing control,
|
||||
and miscellaneous control in mmsys partition.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^syscon@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-mmsys
|
||||
- mediatek,mt2712-mmsys
|
||||
- mediatek,mt6765-mmsys
|
||||
- mediatek,mt6779-mmsys
|
||||
- mediatek,mt6797-mmsys
|
||||
- mediatek,mt8167-mmsys
|
||||
- mediatek,mt8173-mmsys
|
||||
- mediatek,mt8183-mmsys
|
||||
- mediatek,mt8365-mmsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-mmsys
|
||||
- const: mediatek,mt2701-mmsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0x14000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -31,6 +31,7 @@ description: |
|
||||
ipq6018
|
||||
ipq8074
|
||||
mdm9615
|
||||
msm8226
|
||||
msm8916
|
||||
msm8974
|
||||
msm8992
|
||||
@@ -114,6 +115,11 @@ properties:
|
||||
- qcom,apq8084-sbc
|
||||
- const: qcom,apq8084
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,s3ve3g
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,msm8960-cdp
|
||||
@@ -129,6 +135,8 @@ properties:
|
||||
- const: qcom,msm8974
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- alcatel,idol347
|
||||
- const: qcom,msm8916-mtp/1
|
||||
- const: qcom,msm8916-mtp
|
||||
- const: qcom,msm8916
|
||||
@@ -181,6 +189,8 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc7280-idp
|
||||
- qcom,sc7280-idp2
|
||||
- google,piglin
|
||||
- google,senor
|
||||
- const: qcom,sc7280
|
||||
|
||||
|
||||
@@ -238,7 +238,8 @@ properties:
|
||||
- const: renesas,r8a77961
|
||||
|
||||
- description: Kingfisher (SBEV-RCAR-KF-M03)
|
||||
items:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: shimafuji,kingfisher
|
||||
- enum:
|
||||
- renesas,h3ulcb
|
||||
@@ -249,6 +250,17 @@ properties:
|
||||
- renesas,r8a7796
|
||||
- renesas,r8a77961
|
||||
- renesas,r8a77965
|
||||
- items:
|
||||
- const: shimafuji,kingfisher
|
||||
- enum:
|
||||
- renesas,h3ulcb
|
||||
- renesas,m3ulcb
|
||||
- enum:
|
||||
- renesas,r8a779m1
|
||||
- renesas,r8a779m3
|
||||
- enum:
|
||||
- renesas,r8a7795
|
||||
- renesas,r8a77961
|
||||
|
||||
- description: R-Car M3-N (R8A77965)
|
||||
items:
|
||||
@@ -296,6 +308,22 @@ properties:
|
||||
- const: renesas,falcon-cpu
|
||||
- const: renesas,r8a779a0
|
||||
|
||||
- description: R-Car H3e-2G (R8A779M1)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
|
||||
- const: renesas,r8a779m1
|
||||
- const: renesas,r8a7795
|
||||
|
||||
- description: R-Car M3e-2G (R8A779M3)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro)
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
|
||||
- const: renesas,r8a779m3
|
||||
- const: renesas,r8a77961
|
||||
|
||||
- description: RZ/N1D (R9A06G032)
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@@ -111,6 +111,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2771-0000
|
||||
- nvidia,p3509-0000+p3636-0001
|
||||
- const: nvidia,tegra186
|
||||
- items:
|
||||
- enum:
|
||||
|
||||
@@ -1,30 +0,0 @@
|
||||
* Samsung AHCI SATA Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains "samsung,exynos5-sata"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
- samsung,sata-freq : <frequency in MHz>
|
||||
- phys : Must contain exactly one entry as specified
|
||||
in phy-bindings.txt
|
||||
- phy-names : Must be "sata-phy"
|
||||
|
||||
Optional properties:
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names : Shall be "sata" for the external SATA bus clock,
|
||||
and "sclk_sata" for the internal controller clock.
|
||||
|
||||
Example:
|
||||
sata@122f0000 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
samsung,sata-freq = <66>;
|
||||
reg = <0x122f0000 0x1ff>;
|
||||
interrupts = <0 115 0>;
|
||||
clocks = <&clock 277>, <&clock 143>;
|
||||
clock-names = "sata", "sclk_sata";
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
@@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel IXP4xx CompactFlash Card Controller
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
The IXP4xx network processors have a CompactFlash interface that presents
|
||||
a CompactFlash card to the system as a true IDE (parallel ATA) device. The
|
||||
device is always connected to the expansion bus of the IXP4xx SoCs using one
|
||||
or two chip select areas and address translating logic on the board. The
|
||||
node must be placed inside a chip select node on the IXP4xx expansion bus.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,ixp4xx-compact-flash
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Command interface registers
|
||||
- description: Control interface registers
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- $ref: pata-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
bus@c4000000 {
|
||||
compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
|
||||
reg = <0xc4000000 0x1000>;
|
||||
native-endian;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
|
||||
dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
|
||||
ide@1,0 {
|
||||
compatible = "intel,ixp4xx-compact-flash";
|
||||
reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/auxdisplay/arm,versatile-lcd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Character LCD
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description:
|
||||
This binding defines the character LCD interface found on ARM Versatile AB
|
||||
and PB reference platforms.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,versatile-lcd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
};
|
||||
@@ -1,18 +0,0 @@
|
||||
ARM Versatile Character LCD
|
||||
-----------------------------------------------------
|
||||
This binding defines the character LCD interface found on ARM Versatile AB
|
||||
and PB reference platforms.
|
||||
|
||||
Required properties:
|
||||
- compatible : "arm,versatile-clcd"
|
||||
- reg : Location and size of character LCD registers
|
||||
|
||||
Optional properties:
|
||||
- interrupts - single interrupt for character LCD. The character LCD can
|
||||
operate in polled mode without an interrupt.
|
||||
|
||||
Example:
|
||||
lcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/auxdisplay/img,ascii-lcd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASCII LCD displays on Imagination Technologies boards
|
||||
|
||||
maintainers:
|
||||
- Paul Burton <paulburton@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- img,boston-lcd
|
||||
- mti,malta-lcd
|
||||
- mti,sead3-lcd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset in bytes to the LCD registers within the system controller
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- reg
|
||||
- required:
|
||||
- offset
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: img,boston-lcd
|
||||
then:
|
||||
required:
|
||||
- reg
|
||||
else:
|
||||
required:
|
||||
- offset
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lcd: lcd@17fff000 {
|
||||
compatible = "img,boston-lcd";
|
||||
reg = <0x17fff000 0x8>;
|
||||
};
|
||||
@@ -1,17 +0,0 @@
|
||||
Binding for ASCII LCD displays on Imagination Technologies boards
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of:
|
||||
"img,boston-lcd"
|
||||
"mti,malta-lcd"
|
||||
"mti,sead3-lcd"
|
||||
|
||||
Required properties for "img,boston-lcd":
|
||||
- reg : memory region locating the device registers
|
||||
|
||||
Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
|
||||
- regmap: phandle of the system controller containing the LCD registers
|
||||
- offset: offset in bytes to the LCD registers within the system controller
|
||||
|
||||
The layout of the registers & properties of the display are determined
|
||||
from the compatible string, making this binding somewhat trivial.
|
||||
@@ -0,0 +1,168 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel IXP4xx Expansion Bus Controller
|
||||
|
||||
description: |
|
||||
The IXP4xx expansion bus controller handles access to devices on the
|
||||
memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
|
||||
including IXP42x, IXP43x, IXP45x and IXP46x.
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: '^bus@[0-9a-f]+$'
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- intel,ixp42x-expansion-bus-controller
|
||||
- intel,ixp43x-expansion-bus-controller
|
||||
- intel,ixp45x-expansion-bus-controller
|
||||
- intel,ixp46x-expansion-bus-controller
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
description: Control registers for the expansion bus, these are not
|
||||
inside the memory range handled by the expansion bus.
|
||||
maxItems: 1
|
||||
|
||||
native-endian:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: The IXP4xx has a peculiar MMIO access scheme, as it changes
|
||||
the access pattern for words (swizzling) on the bus depending on whether
|
||||
the SoC is running in big-endian or little-endian mode. Thus the
|
||||
registers must always be accessed using native endianness.
|
||||
|
||||
"#address-cells":
|
||||
description: |
|
||||
The first cell is the chip select number.
|
||||
The second cell is the address offset within the bank.
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges: true
|
||||
dma-ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-7],[0-9a-f]+$":
|
||||
description: Devices attached to chip selects are represented as
|
||||
subnodes.
|
||||
type: object
|
||||
|
||||
properties:
|
||||
intel,ixp4xx-eb-t1:
|
||||
description: Address timing, extend address phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
intel,ixp4xx-eb-t2:
|
||||
description: Setup chip select timing, extend setup phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
intel,ixp4xx-eb-t3:
|
||||
description: Strobe timing, extend strobe phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
|
||||
intel,ixp4xx-eb-t4:
|
||||
description: Hold timing, extend hold phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
intel,ixp4xx-eb-t5:
|
||||
description: Recovery timing, extend recovery phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
|
||||
intel,ixp4xx-eb-cycle-type:
|
||||
description: The type of cycles to use on the expansion bus for this
|
||||
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
|
||||
intel,ixp4xx-eb-byte-access-on-halfword:
|
||||
description: Allow byte read access on half word devices.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-hpi-hrdy-pol-high:
|
||||
description: Set HPI HRDY polarity to active high when using HPI.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-mux-address-and-data:
|
||||
description: Multiplex address and data on the data bus.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-ahb-split-transfers:
|
||||
description: Enable AHB split transfers.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-write-enable:
|
||||
description: Enable write cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-byte-access:
|
||||
description: Expansion bus uses only 8 bits. The default is to use
|
||||
16 bits.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- native-endian
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
- dma-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
bus@50000000 {
|
||||
compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
|
||||
reg = <0xc4000000 0x28>;
|
||||
native-endian;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x50000000 0x01000000>,
|
||||
<1 0x0 0x51000000 0x01000000>;
|
||||
dma-ranges = <0 0x0 0x50000000 0x01000000>,
|
||||
<1 0x0 0x51000000 0x01000000>;
|
||||
flash@0,0 {
|
||||
compatible = "intel,ixp4xx-flash", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0x00000000 0x1000000>;
|
||||
intel,ixp4xx-eb-t3 = <3>;
|
||||
intel,ixp4xx-eb-cycle-type = <0>;
|
||||
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
|
||||
intel,ixp4xx-eb-write-enable = <1>;
|
||||
intel,ixp4xx-eb-byte-access = <0>;
|
||||
};
|
||||
serial@1,0 {
|
||||
compatible = "exar,xr16l2551", "ns8250";
|
||||
reg = <1 0x00000000 0x10>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-frequency = <1843200>;
|
||||
intel,ixp4xx-eb-t3 = <3>;
|
||||
intel,ixp4xx-eb-cycle-type = <1>;
|
||||
intel,ixp4xx-eb-write-enable = <1>;
|
||||
intel,ixp4xx-eb-byte-access = <1>;
|
||||
};
|
||||
};
|
||||
@@ -79,9 +79,9 @@ a different secondary CPU release mechanism)
|
||||
linux,usable-memory-range
|
||||
-------------------------
|
||||
|
||||
This property (arm64 only) holds a base address and size, describing a
|
||||
limited region in which memory may be considered available for use by
|
||||
the kernel. Memory outside of this range is not available for use.
|
||||
This property holds a base address and size, describing a limited region in
|
||||
which memory may be considered available for use by the kernel. Memory outside
|
||||
of this range is not available for use.
|
||||
|
||||
This property describes a limitation: memory within this range is only
|
||||
valid when also described through another mechanism that the kernel
|
||||
@@ -106,9 +106,9 @@ respectively, of the root node.
|
||||
linux,elfcorehdr
|
||||
----------------
|
||||
|
||||
This property (currently used only on arm64) holds the memory range,
|
||||
the address and the size, of the elf core header which mainly describes
|
||||
the panicked kernel's memory layout as PT_LOAD segments of elf format.
|
||||
This property holds the memory range, the address and the size, of the elf
|
||||
core header which mainly describes the panicked kernel's memory layout as
|
||||
PT_LOAD segments of elf format.
|
||||
e.g.
|
||||
|
||||
/ {
|
||||
|
||||
@@ -1,26 +0,0 @@
|
||||
|
||||
* Samsung Exynos NoC (Network on Chip) Probe device
|
||||
|
||||
The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.
|
||||
NoC provides the primitive values to get the performance data. The packets
|
||||
that the Network on Chip (NoC) probes detects are transported over
|
||||
the network infrastructure to observer units. You can configure probes to
|
||||
capture packets with header or data on the data request response network,
|
||||
or as traffic debug or statistic collectors. Exynos542x bus has multiple
|
||||
NoC probes to provide bandwidth information about behavior of the SoC
|
||||
that you can use while analyzing system performance.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "samsung,exynos5420-nocp"
|
||||
- reg: physical base address of each NoC Probe and length of memory mapped region.
|
||||
|
||||
Optional properties:
|
||||
- clock-names : the name of clock used by the NoC Probe, "nocp"
|
||||
- clocks : phandles for clock specified in "clock-names" property
|
||||
|
||||
Example : NoC Probe nodes in Device Tree are listed below.
|
||||
|
||||
nocp_mem0_0: nocp@10ca1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1000 0x200>;
|
||||
};
|
||||
@@ -1,169 +0,0 @@
|
||||
|
||||
* Samsung Exynos PPMU (Platform Performance Monitoring Unit) device
|
||||
|
||||
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
|
||||
each IP. PPMU provides the primitive values to get performance data. These
|
||||
PPMU events provide information of the SoC's behaviors so that you may
|
||||
use to analyze system performance, to make behaviors visible and to count
|
||||
usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
|
||||
The Exynos PPMU driver uses the devfreq-event class to provide event data
|
||||
to various devfreq devices. The devfreq devices would use the event data when
|
||||
derterming the current state of each IP.
|
||||
|
||||
Required properties for PPMU device:
|
||||
- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
|
||||
- reg: physical base address of each PPMU and length of memory mapped region.
|
||||
|
||||
Optional properties for PPMU device:
|
||||
- clock-names : the name of clock used by the PPMU, "ppmu"
|
||||
- clocks : phandles for clock specified in "clock-names" property
|
||||
|
||||
Required properties for 'events' child node of PPMU device:
|
||||
- event-name : the unique event name among PPMU device
|
||||
Optional properties for 'events' child node of PPMU device:
|
||||
- event-data-type : Define the type of data which shell be counted
|
||||
by the counter. You can check include/dt-bindings/pmu/exynos_ppmu.h for
|
||||
all possible type, i.e. count read requests, count write data in bytes,
|
||||
etc. This field is optional and when it is missing, the driver code
|
||||
will use default data type.
|
||||
|
||||
Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
|
||||
|
||||
ppmu_dmc0: ppmu_dmc0@106a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106a0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_dmc1: ppmu_dmc1@106b0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106b0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_cpu: ppmu_cpu@106c0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106c0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_rightbus: ppmu_rightbus@112a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x112a0000 0x2000>;
|
||||
clocks = <&cmu CLK_PPMURIGHT>;
|
||||
clock-names = "ppmu";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_leftbus: ppmu_leftbus0@116a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x116a0000 0x2000>;
|
||||
clocks = <&cmu CLK_PPMULEFT>;
|
||||
clock-names = "ppmu";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_2: ppmu-event2-dmc0 {
|
||||
event-name = "ppmu-event2-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_1: ppmu-event1-dmc0 {
|
||||
event-name = "ppmu-event1-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_0: ppmu-event0-dmc0 {
|
||||
event-name = "ppmu-event0-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_dmc1 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc1_3: ppmu-event3-dmc1 {
|
||||
event-name = "ppmu-event3-dmc1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_leftbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_leftbus_3: ppmu-event3-leftbus {
|
||||
event-name = "ppmu-event3-leftbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_rightbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
|
||||
|
||||
ppmu_d0_cpu: ppmu_d0_cpu@10480000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x10480000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_d0_general: ppmu_d0_general@10490000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x10490000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_d0_rt: ppmu_d0_rt@104a0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104a0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_d1_cpu: ppmu_d1_cpu@104b0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104b0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_d1_general: ppmu_d1_general@104c0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104c0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_d1_rt: ppmu_d1_rt@104d0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104d0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Example4 : 'event-data-type' in exynos4412-ppmu-common.dtsi are listed below.
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
event-data-type = <(PPMU_RO_DATA_CNT |
|
||||
PPMU_WO_DATA_CNT)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos NoC (Network on Chip) Probe
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
|
||||
NoC provides the primitive values to get the performance data. The packets
|
||||
that the Network on Chip (NoC) probes detects are transported over the
|
||||
network infrastructure to observer units. You can configure probes to capture
|
||||
packets with header or data on the data request response network, or as
|
||||
traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
|
||||
to provide bandwidth information about behavior of the SoC that you can use
|
||||
while analyzing system performance.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,exynos5420-nocp
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nocp
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
nocp_mem0_0: nocp@10ca1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10ca1000 0x200>;
|
||||
};
|
||||
@@ -0,0 +1,169 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
|
||||
each IP. PPMU provides the primitive values to get performance data. These
|
||||
PPMU events provide information of the SoC's behaviors so that you may use to
|
||||
analyze system performance, to make behaviors visible and to count usages of
|
||||
each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
|
||||
Exynos PPMU driver uses the devfreq-event class to provide event data to
|
||||
various devfreq devices. The devfreq devices would use the event data when
|
||||
derterming the current state of each IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos-ppmu
|
||||
- samsung,exynos-ppmu-v2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ppmu
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
events:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
'^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
|
||||
type: object
|
||||
properties:
|
||||
event-name:
|
||||
description: |
|
||||
The unique event name among PPMU device
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
|
||||
event-data-type:
|
||||
description: |
|
||||
Define the type of data which shell be counted by the counter.
|
||||
You can check include/dt-bindings/pmu/exynos_ppmu.h for all
|
||||
possible type, i.e. count read requests, count write data in
|
||||
bytes, etc. This field is optional and when it is missing, the
|
||||
driver code will use default data type.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- event-name
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
|
||||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
ppmu_dmc0: ppmu@106a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106a0000 0x2000>;
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_2: ppmu-event2-dmc0 {
|
||||
event-name = "ppmu-event2-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_1: ppmu-event1-dmc0 {
|
||||
event-name = "ppmu-event1-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_0: ppmu-event0-dmc0 {
|
||||
event-name = "ppmu-event0-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppmu_rightbus: ppmu@112a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x112a0000 0x2000>;
|
||||
clocks = <&cmu CLK_PPMURIGHT>;
|
||||
clock-names = "ppmu";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// PPMUv2 nodes in Exynos5433
|
||||
ppmu_d0_cpu: ppmu@10480000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x10480000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d0_general: ppmu@10490000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x10490000 0x2000>;
|
||||
|
||||
events {
|
||||
ppmu_event0_d0_general: ppmu-event0-d0-general {
|
||||
event-name = "ppmu-event0-d0-general";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppmu_d0_rt: ppmu@104a0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104a0000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d1_cpu: ppmu@104b0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104b0000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d1_general: ppmu@104c0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104c0000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d1_rt: ppmu@104d0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104d0000 0x2000>;
|
||||
};
|
||||
|
||||
- |
|
||||
// PPMUv1 nodes with event-data-type for Exynos4412
|
||||
#include <dt-bindings/pmu/exynos_ppmu.h>
|
||||
|
||||
ppmu@106a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106a0000 0x2000>;
|
||||
clocks = <&clock 400>;
|
||||
clock-names = "ppmu";
|
||||
|
||||
events {
|
||||
ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
event-data-type = <(PPMU_RO_DATA_CNT |
|
||||
PPMU_WO_DATA_CNT)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -174,7 +174,6 @@ examples:
|
||||
phy-names = "phy";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pins>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
@@ -233,7 +232,6 @@ examples:
|
||||
phy-names = "phy";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pins>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
||||
@@ -37,7 +37,8 @@ properties:
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: Video port for MIPI DSI Channel-A input
|
||||
|
||||
properties:
|
||||
@@ -57,7 +58,8 @@ properties:
|
||||
- const: 4
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: Video port for MIPI DSI Channel-B input
|
||||
|
||||
properties:
|
||||
|
||||
@@ -27,6 +27,7 @@ properties:
|
||||
- fsl,imx6ul-lcdif
|
||||
- fsl,imx7d-lcdif
|
||||
- fsl,imx8mm-lcdif
|
||||
- fsl,imx8mn-lcdif
|
||||
- fsl,imx8mq-lcdif
|
||||
- const: fsl,imx6sx-lcdif
|
||||
|
||||
|
||||
@@ -89,7 +89,8 @@ properties:
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
$ref: "/schemas/graph.yaml#/$defs/port-base"
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
Input endpoints of the controller.
|
||||
properties:
|
||||
@@ -104,7 +105,8 @@ properties:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
port@1:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
$ref: "/schemas/graph.yaml#/$defs/port-base"
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
Output endpoints of the controller.
|
||||
properties:
|
||||
|
||||
@@ -14,9 +14,9 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-10nm
|
||||
- const: qcom,dsi-phy-10nm-8998
|
||||
enum:
|
||||
- qcom,dsi-phy-10nm
|
||||
- qcom,dsi-phy-10nm-8998
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@@ -14,9 +14,9 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-14nm
|
||||
- const: qcom,dsi-phy-14nm-660
|
||||
enum:
|
||||
- qcom,dsi-phy-14nm
|
||||
- qcom,dsi-phy-14nm-660
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@@ -14,8 +14,7 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-20nm
|
||||
const: qcom,dsi-phy-20nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@@ -14,10 +14,10 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-28nm-hpm
|
||||
- const: qcom,dsi-phy-28nm-lp
|
||||
- const: qcom,dsi-phy-28nm-8960
|
||||
enum:
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
- qcom,dsi-phy-28nm-8960
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@@ -70,7 +70,6 @@ examples:
|
||||
avee-supply = <&ppvarp_lcd>;
|
||||
pp1800-supply = <&pp1800_lcd>;
|
||||
backlight = <&backlight_lcd0>;
|
||||
status = "okay";
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
|
||||
@@ -1,120 +0,0 @@
|
||||
ZTE VOU Display Controller
|
||||
|
||||
This is a display controller found on ZTE ZX296718 SoC. It includes multiple
|
||||
Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
|
||||
handling scaling, color space conversion etc. VOU also integrates the support
|
||||
for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
|
||||
|
||||
* Master VOU node
|
||||
|
||||
It must be the parent node of all the sub-device nodes.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-vou"
|
||||
- #address-cells: should be <1>
|
||||
- #size-cells: should be <1>
|
||||
- ranges: list of address translations between VOU and sub-devices
|
||||
|
||||
* VOU DPC device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-dpc"
|
||||
- reg: Physical base address and length of DPC register regions, one for each
|
||||
entry in 'reg-names'
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
"osd"
|
||||
"timing_ctrl"
|
||||
"dtrc"
|
||||
"vou_ctrl"
|
||||
"otfppu"
|
||||
- interrupts: VOU DPC interrupt number to CPU
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each entry
|
||||
in 'clock-names'
|
||||
- clock-names: A list of clock names. The following clocks are required:
|
||||
"aclk"
|
||||
"ppu_wclk"
|
||||
"main_wclk"
|
||||
"aux_wclk"
|
||||
|
||||
* HDMI output device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-hdmi"
|
||||
- reg: Physical base address and length of the HDMI device IO region
|
||||
- interrupts : HDMI interrupt number to CPU
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each entry
|
||||
in 'clock-names'
|
||||
- clock-names: A list of clock names. The following clocks are required:
|
||||
"osc_cec"
|
||||
"osc_clk"
|
||||
"xclk"
|
||||
|
||||
* TV Encoder output device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-tvenc"
|
||||
- reg: Physical base address and length of the TVENC device IO region
|
||||
- zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
|
||||
integer cells. The first cell is the offset of SYSCTRL register used
|
||||
to control TV Encoder DAC power, and the second cell is the bit mask.
|
||||
|
||||
* VGA output device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-vga"
|
||||
- reg: Physical base address and length of the VGA device IO region
|
||||
- interrupts : VGA interrupt number to CPU
|
||||
- clocks: Phandle with clock-specifier pointing to VGA I2C clock.
|
||||
- clock-names: Must be "i2c_wclk".
|
||||
- zte,vga-power-control: the phandle to SYSCTRL block followed by two
|
||||
integer cells. The first cell is the offset of SYSCTRL register used
|
||||
to control VGA DAC power, and the second cell is the bit mask.
|
||||
|
||||
Example:
|
||||
|
||||
vou: vou@1440000 {
|
||||
compatible = "zte,zx296718-vou";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1440000 0x10000>;
|
||||
|
||||
dpc: dpc@0 {
|
||||
compatible = "zte,zx296718-dpc";
|
||||
reg = <0x0000 0x1000>, <0x1000 0x1000>,
|
||||
<0x5000 0x1000>, <0x6000 0x1000>,
|
||||
<0xa000 0x1000>;
|
||||
reg-names = "osd", "timing_ctrl",
|
||||
"dtrc", "vou_ctrl",
|
||||
"otfppu";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
|
||||
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
|
||||
clock-names = "aclk", "ppu_wclk",
|
||||
"main_wclk", "aux_wclk";
|
||||
};
|
||||
|
||||
vga: vga@8000 {
|
||||
compatible = "zte,zx296718-vga";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topcrm VGA_I2C_WCLK>;
|
||||
clock-names = "i2c_wclk";
|
||||
zte,vga-power-control = <&sysctrl 0x170 0xe0>;
|
||||
};
|
||||
|
||||
hdmi: hdmi@c000 {
|
||||
compatible = "zte,zx296718-hdmi";
|
||||
reg = <0xc000 0x4000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&topcrm HDMI_OSC_CEC>,
|
||||
<&topcrm HDMI_OSC_CLK>,
|
||||
<&topcrm HDMI_XCLK>;
|
||||
clock-names = "osc_cec", "osc_clk", "xclk";
|
||||
};
|
||||
|
||||
tvenc: tvenc@2000 {
|
||||
compatible = "zte,zx296718-tvenc";
|
||||
reg = <0x2000 0x1000>;
|
||||
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
|
||||
};
|
||||
};
|
||||
@@ -19,12 +19,12 @@ properties:
|
||||
description: The cell is the request line number.
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: allwinner,sun6i-a31-dma
|
||||
- const: allwinner,sun8i-a23-dma
|
||||
- const: allwinner,sun8i-a83t-dma
|
||||
- const: allwinner,sun8i-h3-dma
|
||||
- const: allwinner,sun8i-v3s-dma
|
||||
enum:
|
||||
- allwinner,sun6i-a31-dma
|
||||
- allwinner,sun8i-a23-dma
|
||||
- allwinner,sun8i-a83t-dma
|
||||
- allwinner,sun8i-h3-dma
|
||||
- allwinner,sun8i-v3s-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -9,6 +9,7 @@ Required properties:
|
||||
"fsl,imx53-sdma"
|
||||
"fsl,imx6q-sdma"
|
||||
"fsl,imx7d-sdma"
|
||||
"fsl,imx6ul-sdma"
|
||||
"fsl,imx8mq-sdma"
|
||||
"fsl,imx8mm-sdma"
|
||||
"fsl,imx8mn-sdma"
|
||||
|
||||
@@ -34,6 +34,10 @@ properties:
|
||||
- description: SCMI compliant firmware with ARM SMC/HVC transport
|
||||
items:
|
||||
- const: arm,scmi-smc
|
||||
- description: SCMI compliant firmware with SCMI Virtio transport.
|
||||
The virtio transport only supports a single device.
|
||||
items:
|
||||
- const: arm,scmi-virtio
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
@@ -172,6 +176,7 @@ patternProperties:
|
||||
Each sub-node represents a protocol supported. If the platform
|
||||
supports a dedicated communication channel for a particular protocol,
|
||||
then the corresponding transport properties must be present.
|
||||
The virtio transport does not support a dedicated communication channel.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
@@ -195,7 +200,6 @@ patternProperties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- shmem
|
||||
|
||||
if:
|
||||
properties:
|
||||
@@ -209,6 +213,7 @@ then:
|
||||
|
||||
required:
|
||||
- mboxes
|
||||
- shmem
|
||||
|
||||
else:
|
||||
if:
|
||||
@@ -219,6 +224,7 @@ else:
|
||||
then:
|
||||
required:
|
||||
- arm,smc-id
|
||||
- shmem
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@@ -131,9 +131,9 @@ properties:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: arm,scpi-dvfs-clocks
|
||||
- const: arm,scpi-variable-clocks
|
||||
enum:
|
||||
- arm,scpi-dvfs-clocks
|
||||
- arm,scpi-variable-clocks
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@@ -1,25 +0,0 @@
|
||||
Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
|
||||
The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
|
||||
Programmable Logic (PL). The configuration uses the firmware interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain "xlnx,zynqmp-pcap-fpga"
|
||||
|
||||
Example for full FPGA configuration:
|
||||
|
||||
fpga-region0 {
|
||||
compatible = "fpga-region";
|
||||
fpga-mgr = <&zynqmp_pcap>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
method = "smc";
|
||||
zynqmp_pcap: pcap {
|
||||
compatible = "xlnx,zynqmp-pcap-fpga";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Nava kishore Manne <navam@xilinx.com>
|
||||
|
||||
description: |
|
||||
Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
|
||||
The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
|
||||
configure the Programmable Logic (PL). The configuration uses the
|
||||
firmware interface.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: xlnx,zynqmp-pcap-fpga
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
zynqmp_pcap: pcap {
|
||||
compatible = "xlnx,zynqmp-pcap-fpga";
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
77
Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
Normal file
77
Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
Normal file
@@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Aspeed SGPIO controller
|
||||
|
||||
maintainers:
|
||||
- Andrew Jeffery <andrew@aj.id.au>
|
||||
|
||||
description:
|
||||
This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
|
||||
AST2600 have two sgpio master one with 128 pins another one with 80 pins,
|
||||
AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
|
||||
GPIO pins can be programmed to support the following options
|
||||
- Support interrupt option for each input port and various interrupt
|
||||
sensitivity option (level-high, level-low, edge-high, edge-low)
|
||||
- Support reset tolerance option for each output port
|
||||
- Directly connected to APB bus and its shift clock is from APB bus clock
|
||||
divided by a programmable value.
|
||||
- Co-work with external signal-chained TTL components (74LV165/74LV595)
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2400-sgpio
|
||||
- aspeed,ast2500-sgpio
|
||||
- aspeed,ast2600-sgpiom
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
ngpios: true
|
||||
|
||||
bus-frequency: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- ngpios
|
||||
- clocks
|
||||
- bus-frequency
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/aspeed-clock.h>
|
||||
sgpio: sgpio@1e780200 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "aspeed,ast2500-sgpio";
|
||||
gpio-controller;
|
||||
interrupts = <40>;
|
||||
reg = <0x1e780200 0x0100>;
|
||||
clocks = <&syscon ASPEED_CLK_APB>;
|
||||
interrupt-controller;
|
||||
ngpios = <80>;
|
||||
bus-frequency = <12000000>;
|
||||
};
|
||||
@@ -1,46 +0,0 @@
|
||||
Aspeed SGPIO controller Device Tree Bindings
|
||||
--------------------------------------------
|
||||
|
||||
This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
|
||||
featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
|
||||
support the following options:
|
||||
- Support interrupt option for each input port and various interrupt
|
||||
sensitivity option (level-high, level-low, edge-high, edge-low)
|
||||
- Support reset tolerance option for each output port
|
||||
- Directly connected to APB bus and its shift clock is from APB bus clock
|
||||
divided by a programmable value.
|
||||
- Co-work with external signal-chained TTL components (74LV165/74LV595)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be one of
|
||||
"aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
|
||||
- #gpio-cells : Should be 2, see gpio.txt
|
||||
- reg : Address and length of the register set for the device
|
||||
- gpio-controller : Marks the device node as a GPIO controller
|
||||
- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
|
||||
- interrupt-controller : Mark the GPIO controller as an interrupt-controller
|
||||
- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
|
||||
2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
|
||||
output. Up to 80 pins, must be a multiple of 8.
|
||||
- clocks : A phandle to the APB clock for SGPM clock division
|
||||
- bus-frequency : SGPM CLK frequency
|
||||
|
||||
The sgpio and interrupt properties are further described in their respective
|
||||
bindings documentation:
|
||||
|
||||
- Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
|
||||
Example:
|
||||
sgpio: sgpio@1e780200 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "aspeed,ast2500-sgpio";
|
||||
gpio-controller;
|
||||
interrupts = <40>;
|
||||
reg = <0x1e780200 0x0100>;
|
||||
clocks = <&syscon ASPEED_CLK_APB>;
|
||||
interrupt-controller;
|
||||
ngpios = <8>;
|
||||
bus-frequency = <12000000>;
|
||||
};
|
||||
@@ -20,6 +20,7 @@ properties:
|
||||
- mediatek,mt8183-mali
|
||||
- realtek,rtd1619-mali
|
||||
- rockchip,px30-mali
|
||||
- rockchip,rk3568-mali
|
||||
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
|
||||
|
||||
reg:
|
||||
|
||||
@@ -1,12 +0,0 @@
|
||||
Bindings for MAX1619 Temperature Sensor
|
||||
|
||||
Required properties:
|
||||
- compatible : "maxim,max1619"
|
||||
- reg : I2C address, one of 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, or
|
||||
0x4d, 0x4e
|
||||
|
||||
Example:
|
||||
temp@4c {
|
||||
compatible = "maxim,max1619";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
@@ -1,46 +0,0 @@
|
||||
Broadcom iProc I2C controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible:
|
||||
Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c"
|
||||
|
||||
- reg:
|
||||
Define the base and range of the I/O address space that contain the iProc
|
||||
I2C controller registers
|
||||
|
||||
- clock-frequency:
|
||||
This is the I2C bus clock. Need to be either 100000 or 400000
|
||||
|
||||
- #address-cells:
|
||||
Always 1 (for I2C addresses)
|
||||
|
||||
- #size-cells:
|
||||
Always 0
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupts:
|
||||
Should contain the I2C interrupt. For certain revisions of the I2C
|
||||
controller, I2C interrupt is unwired to the interrupt controller. In such
|
||||
case, this property should be left unspecified, and driver will fall back
|
||||
to polling mode
|
||||
|
||||
- brcm,ape-hsls-addr-mask:
|
||||
Required for "brcm,iproc-nic-i2c". Host view of address mask into the
|
||||
'APE' co-processor. Value must be unsigned, 32-bit
|
||||
|
||||
Example:
|
||||
i2c0: i2c@18008000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x18008000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
codec: wm8750@1a {
|
||||
compatible = "wlf,wm8750";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
71
Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.yaml
Normal file
71
Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.yaml
Normal file
@@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/brcm,iproc-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom iProc I2C controller
|
||||
|
||||
maintainers:
|
||||
- Rafał Miłecki <rafal@milecki.pl>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,iproc-i2c
|
||||
- brcm,iproc-nic-i2c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
enum: [ 100000, 400000 ]
|
||||
|
||||
interrupts:
|
||||
description: |
|
||||
Should contain the I2C interrupt. For certain revisions of the I2C
|
||||
controller, I2C interrupt is unwired to the interrupt controller. In such
|
||||
case, this property should be left unspecified, and driver will fall back
|
||||
to polling mode
|
||||
maxItems: 1
|
||||
|
||||
brcm,ape-hsls-addr-mask:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Host view of address mask into the 'APE' co-processor
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,iproc-nic-i2c
|
||||
then:
|
||||
required:
|
||||
- brcm,ape-hsls-addr-mask
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- clock-frequency
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
i2c@18008000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x18008000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
wm8750@1a {
|
||||
compatible = "wlf,wm8750";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
@@ -27,14 +27,25 @@ properties:
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Transmit End Interrupt (TEI)
|
||||
- description: Receive Data Full Interrupt (RI)
|
||||
- description: Transmit Data Empty Interrupt (TI)
|
||||
- description: Stop Condition Detection Interrupt (SPI)
|
||||
- description: Start Condition Detection Interrupt (STI)
|
||||
- description: NACK Reception Interrupt (NAKI)
|
||||
- description: Arbitration-Lost Interrupt (ALI)
|
||||
- description: Timeout Interrupt (TMOI)
|
||||
- description: Transmit End Interrupt
|
||||
- description: Receive Data Full Interrupt
|
||||
- description: Transmit Data Empty Interrupt
|
||||
- description: Stop Condition Detection Interrupt
|
||||
- description: Start Condition Detection Interrupt
|
||||
- description: NACK Reception Interrupt
|
||||
- description: Arbitration-Lost Interrupt
|
||||
- description: Timeout Interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: tei
|
||||
- const: ri
|
||||
- const: ti
|
||||
- const: spi
|
||||
- const: sti
|
||||
- const: naki
|
||||
- const: ali
|
||||
- const: tmoi
|
||||
|
||||
clock-frequency:
|
||||
description:
|
||||
@@ -51,6 +62,7 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-frequency
|
||||
- power-domains
|
||||
@@ -85,6 +97,8 @@ examples:
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
|
||||
"tmoi";
|
||||
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
|
||||
clock-frequency = <100000>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
@@ -72,11 +72,11 @@ additionalProperties: false
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,omap2420-i2c
|
||||
- const: ti,omap2430-i2c
|
||||
- const: ti,omap3-i2c
|
||||
- const: ti,omap4-i2c
|
||||
enum:
|
||||
- ti,omap2420-i2c
|
||||
- ti,omap2430-i2c
|
||||
- ti,omap3-i2c
|
||||
- ti,omap4-i2c
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
||||
@@ -19,10 +19,10 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: loongson,liointc-1.0
|
||||
- const: loongson,liointc-1.0a
|
||||
- const: loongson,liointc-2.0
|
||||
enum:
|
||||
- loongson,liointc-1.0
|
||||
- loongson,liointc-1.0a
|
||||
- loongson,liointc-2.0
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
||||
@@ -1,50 +0,0 @@
|
||||
* Samsung Exynos Interrupt Combiner Controller
|
||||
|
||||
Samsung's Exynos4 architecture includes a interrupt combiner controller which
|
||||
can combine interrupt sources as a group and provide a single interrupt request
|
||||
for the group. The interrupt request from each group are connected to a parent
|
||||
interrupt controller, such as GIC in case of Exynos4210.
|
||||
|
||||
The interrupt combiner controller consists of multiple combiners. Up to eight
|
||||
interrupt sources can be connected to a combiner. The combiner outputs one
|
||||
combined interrupt for its eight interrupt sources. The combined interrupt
|
||||
is usually connected to a parent interrupt controller.
|
||||
|
||||
A single node in the device tree is used to describe the interrupt combiner
|
||||
controller module (which includes multiple combiners). A combiner in the
|
||||
interrupt controller module shares config/control registers with other
|
||||
combiners. For example, a 32-bit interrupt enable/disable config register
|
||||
can accommodate up to 4 interrupt combiners (with each combiner supporting
|
||||
up to 8 interrupt sources).
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-combiner".
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: should be <2>. The meaning of the cells are
|
||||
* First Cell: Combiner Group Number.
|
||||
* Second Cell: Interrupt number within the group.
|
||||
- reg: Base address and size of interrupt combiner registers.
|
||||
- interrupts: The list of interrupts generated by the combiners which are then
|
||||
connected to a parent interrupt controller. The format of the interrupt
|
||||
specifier depends in the interrupt parent controller.
|
||||
|
||||
Optional properties:
|
||||
- samsung,combiner-nr: The number of interrupt combiners supported. If this
|
||||
property is not specified, the default number of combiners is assumed
|
||||
to be 16.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
The following is a an example from the Exynos4210 SoC dtsi file.
|
||||
|
||||
combiner:interrupt-controller@10440000 {
|
||||
compatible = "samsung,exynos4210-combiner";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x10440000 0x1000>;
|
||||
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
|
||||
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
|
||||
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
|
||||
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
|
||||
};
|
||||
@@ -0,0 +1,96 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC Interrupt Combiner Controller
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
Samsung's Exynos4 architecture includes a interrupt combiner controller which
|
||||
can combine interrupt sources as a group and provide a single interrupt
|
||||
request for the group. The interrupt request from each group are connected to
|
||||
a parent interrupt controller, such as GIC in case of Exynos4210.
|
||||
|
||||
The interrupt combiner controller consists of multiple combiners. Up to eight
|
||||
interrupt sources can be connected to a combiner. The combiner outputs one
|
||||
combined interrupt for its eight interrupt sources. The combined interrupt is
|
||||
usually connected to a parent interrupt controller.
|
||||
|
||||
A single node in the device tree is used to describe the interrupt combiner
|
||||
controller module (which includes multiple combiners). A combiner in the
|
||||
interrupt controller module shares config/control registers with other
|
||||
combiners. For example, a 32-bit interrupt enable/disable config register can
|
||||
accommodate up to 4 interrupt combiners (with each combiner supporting up to
|
||||
8 interrupt sources).
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,exynos4210-combiner
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 32
|
||||
|
||||
"#interrupt-cells":
|
||||
description: |
|
||||
The meaning of the cells are:
|
||||
* First Cell: Combiner Group Number.
|
||||
* Second Cell: Interrupt number within the group.
|
||||
const: 2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
samsung,combiner-nr:
|
||||
description: |
|
||||
The number of interrupt combiners supported. Should match number
|
||||
of interrupts set in "interrupts" property.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 8
|
||||
maximum: 32
|
||||
default: 16
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- interrupt-controller
|
||||
- interrupts
|
||||
- "#interrupt-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
interrupt-controller@10440000 {
|
||||
compatible = "samsung,exynos4210-combiner";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x10440000 0x1000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
@@ -46,7 +46,7 @@ properties:
|
||||
AM437x family of SoCs,
|
||||
AM57xx family of SoCs
|
||||
66AK2G family of SoCs
|
||||
Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs
|
||||
Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -95,6 +95,8 @@ properties:
|
||||
- AM65x and J721E SoCs have "host_intr5", "host_intr6" and
|
||||
"host_intr7" interrupts connected to MPU, and other ICSSG
|
||||
instances.
|
||||
- AM64x SoCs have all the 8 host interrupts connected to various
|
||||
other SoC entities
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@@ -35,6 +35,10 @@ Optional properties for a client device:
|
||||
start_offset: the start offset of register address that GCE can access.
|
||||
size: the total size of register address that GCE can access.
|
||||
|
||||
Optional properties for a client mutex node:
|
||||
- mediatek,gce-events: GCE events used by clients. The event numbers are
|
||||
defined in 'dt-bindings/gce/<chip>-gce.h'.
|
||||
|
||||
Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
|
||||
'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
|
||||
sub-system ids, thread priority, event ids.
|
||||
@@ -62,3 +66,14 @@ Example for a client device:
|
||||
<&gce SUBSYS_1401XXXX 0x2000 0x100>;
|
||||
...
|
||||
};
|
||||
|
||||
Example for a client mutex node:
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
|
||||
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
|
||||
};
|
||||
|
||||
@@ -44,7 +44,8 @@ properties:
|
||||
const: isc-mck
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Input port node, single endpoint describing the input pad.
|
||||
|
||||
|
||||
@@ -83,10 +83,10 @@ properties:
|
||||
link-frequencies: true
|
||||
data-lanes: true
|
||||
bus-type:
|
||||
oneOf:
|
||||
- const: 1 # CSI-2 C-PHY
|
||||
- const: 3 # CCP2
|
||||
- const: 4 # CSI-2 D-PHY
|
||||
enum:
|
||||
- 1 # CSI-2 C-PHY
|
||||
- 3 # CCP2
|
||||
- 4 # CSI-2 D-PHY
|
||||
|
||||
required:
|
||||
- link-frequencies
|
||||
|
||||
@@ -52,7 +52,7 @@ properties:
|
||||
of the data and clock lines.
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
description:
|
||||
Input port node, single endpoint describing the input pad.
|
||||
|
||||
|
||||
@@ -200,8 +200,6 @@ examples:
|
||||
clock-names = "pclk", "wrap", "phy", "axi";
|
||||
power-domains = <&mipi_pd>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@@ -16,12 +16,17 @@ description: |-
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
# JPEG decoder
|
||||
oneOf:
|
||||
- items:
|
||||
enum:
|
||||
- nxp,imx8qxp-jpgdec
|
||||
# JPEG encoder
|
||||
- nxp,imx8qxp-jpgenc
|
||||
- items:
|
||||
- const: nxp,imx8qm-jpgdec
|
||||
- const: nxp,imx8qxp-jpgdec
|
||||
- items:
|
||||
- const: nxp,imx8qm-jpgenc
|
||||
- const: nxp,imx8qxp-jpgenc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -69,7 +74,7 @@ examples:
|
||||
};
|
||||
|
||||
jpegenc: jpegenc@58450000 {
|
||||
compatible = "nxp,imx8qxp-jpgenc";
|
||||
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
|
||||
reg = <0x58450000 0x00050000 >;
|
||||
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@@ -96,7 +96,7 @@ properties:
|
||||
Indicates that the channel acts as primary among the bonded channels.
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Child port node corresponding to the data input. The port node must
|
||||
@@ -242,7 +242,6 @@ examples:
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 513>;
|
||||
renesas,bonding = <&drif11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif11: rif@e6f70000 {
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
|
||||
|
||||
The DDR controller of the AR7xxx and AR9xxx families provides an interface
|
||||
to flush the FIFO between various devices and the DDR. This is mainly used
|
||||
by the IRQ controller to flush the FIFO before running the interrupt handler
|
||||
of such devices.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: has to be "qca,<soc-type>-ddr-controller",
|
||||
"qca,[ar7100|ar7240]-ddr-controller" as fallback.
|
||||
On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
|
||||
fallback, otherwise "qca,ar7240-ddr-controller" should be used.
|
||||
- reg: Base address and size of the controller's memory area
|
||||
- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
|
||||
the write buffer channel index, should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
ddr_ctrl: memory-controller@18000000 {
|
||||
compatible = "qca,ar9132-ddr-controller",
|
||||
"qca,ar7240-ddr-controller";
|
||||
reg = <0x18000000 0x100>;
|
||||
|
||||
#qca,ddr-wb-channel-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
interrupt-controller {
|
||||
...
|
||||
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
|
||||
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
|
||||
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
|
||||
};
|
||||
@@ -1,27 +0,0 @@
|
||||
DDR PHY Front End (DPFE) for Broadcom STB
|
||||
=========================================
|
||||
|
||||
DPFE and the DPFE firmware provide an interface for the host CPU to
|
||||
communicate with the DCPU, which resides inside the DDR PHY.
|
||||
|
||||
There are three memory regions for interacting with the DCPU. These are
|
||||
specified in a single reg property.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu"
|
||||
or "brcm,dpfe-cpu"
|
||||
- reg: must reference three register ranges
|
||||
- start address and length of the DCPU register space
|
||||
- start address and length of the DCPU data memory space
|
||||
- start address and length of the DCPU instruction memory space
|
||||
- reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem";
|
||||
they must be in the same order as the register declarations
|
||||
|
||||
Example:
|
||||
dpfe_cpu0: dpfe-cpu@f1132000 {
|
||||
compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
|
||||
reg = <0xf1132000 0x180
|
||||
0xf1134000 0x1000
|
||||
0xf1138000 0x4000>;
|
||||
reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
|
||||
};
|
||||
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/brcm,dpfe-cpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: DDR PHY Front End (DPFE) for Broadcom STB
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Markus Mayer <mmayer@broadcom.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm7271-dpfe-cpu
|
||||
- brcm,bcm7268-dpfe-cpu
|
||||
- const: brcm,dpfe-cpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: DCPU register space
|
||||
- description: DCPU data memory space
|
||||
- description: DCPU instruction memory space
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dpfe-cpu
|
||||
- const: dpfe-dmem
|
||||
- const: dpfe-imem
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dpfe-cpu@f1132000 {
|
||||
compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
|
||||
reg = <0xf1132000 0x180>,
|
||||
<0xf1134000 0x1000>,
|
||||
<0xf1138000 0x4000>;
|
||||
reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
|
||||
};
|
||||
@@ -1,84 +0,0 @@
|
||||
* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
|
||||
|
||||
The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
|
||||
memory chips are connected. The driver is to monitor the controller in runtime
|
||||
and switch frequency and voltage. To monitor the usage of the controller in
|
||||
runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
|
||||
is able to measure the current load of the memory.
|
||||
When 'userspace' governor is used for the driver, an application is able to
|
||||
switch the DMC and memory frequency.
|
||||
|
||||
Required properties for DMC device for Exynos5422:
|
||||
- compatible: Should be "samsung,exynos5422-dmc".
|
||||
- clocks : list of clock specifiers, must contain an entry for each
|
||||
required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
|
||||
CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
|
||||
CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
|
||||
- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
|
||||
"fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
|
||||
"mout_mclk_cdrex" entries
|
||||
- devfreq-events : phandles for PPMU devices connected to this DMC.
|
||||
- vdd-supply : phandle for voltage regulator which is connected.
|
||||
- reg : registers of two CDREX controllers.
|
||||
- operating-points-v2 : phandle for OPPs described in v2 definition.
|
||||
- device-handle : phandle of the connected DRAM memory device. For more
|
||||
information please refer to documentation file:
|
||||
Documentation/devicetree/bindings/ddr/lpddr3.txt
|
||||
- devfreq-events : phandles of the PPMU events used by the controller.
|
||||
- samsung,syscon-clk : phandle of the clock register set used by the controller,
|
||||
these registers are used for enabling a 'pause' feature and are not
|
||||
exposed by clock framework but they must be used in a safe way.
|
||||
The register offsets are in the driver code and specyfic for this SoC
|
||||
type.
|
||||
|
||||
Optional properties for DMC device for Exynos5422:
|
||||
- interrupt-parent : The parent interrupt controller.
|
||||
- interrupts : Contains the IRQ line numbers for the DMC internal performance
|
||||
event counters in DREX0 and DREX1 channels. Align with specification of the
|
||||
interrupt line(s) in the interrupt-parent controller.
|
||||
- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
|
||||
same as in the 'interrupts' list above.
|
||||
|
||||
Example:
|
||||
|
||||
ppmu_dmc0_0: ppmu@10d00000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x10d00000 0x2000>;
|
||||
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
|
||||
clock-names = "ppmu";
|
||||
events {
|
||||
ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
|
||||
event-name = "ppmu-event3-dmc0_0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dmc: memory-controller@10c20000 {
|
||||
compatible = "samsung,exynos5422-dmc";
|
||||
reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
|
||||
clocks = <&clock CLK_FOUT_SPLL>,
|
||||
<&clock CLK_MOUT_SCLK_SPLL>,
|
||||
<&clock CLK_FF_DOUT_SPLL2>,
|
||||
<&clock CLK_FOUT_BPLL>,
|
||||
<&clock CLK_MOUT_BPLL>,
|
||||
<&clock CLK_SCLK_BPLL>,
|
||||
<&clock CLK_MOUT_MX_MSPLL_CCORE>,
|
||||
<&clock CLK_MOUT_MCLK_CDREX>;
|
||||
clock-names = "fout_spll",
|
||||
"mout_sclk_spll",
|
||||
"ff_dout_spll2",
|
||||
"fout_bpll",
|
||||
"mout_bpll",
|
||||
"sclk_bpll",
|
||||
"mout_mx_mspll_ccore",
|
||||
"mout_mclk_cdrex";
|
||||
operating-points-v2 = <&dmc_opp_table>;
|
||||
devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
|
||||
<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
|
||||
device-handle = <&samsung_K3QF2F20DB>;
|
||||
vdd-supply = <&buck1_reg>;
|
||||
samsung,syscon-clk = <&clock>;
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <16 0>, <16 1>;
|
||||
interrupt-names = "drex_0", "drex_1";
|
||||
};
|
||||
@@ -0,0 +1,31 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell MVEBU SDRAM controller
|
||||
|
||||
maintainers:
|
||||
- Jan Luebbe <jlu@pengutronix.de>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,armada-xp-sdram-controller
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
memory-controller@1400 {
|
||||
compatible = "marvell,armada-xp-sdram-controller";
|
||||
reg = <0x1400 0x500>;
|
||||
};
|
||||
@@ -1,21 +0,0 @@
|
||||
Device Tree bindings for MVEBU SDRAM controllers
|
||||
|
||||
The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
|
||||
differs from one SoC variant to another, but they also share a number
|
||||
of commonalities.
|
||||
|
||||
For now, this Device Tree binding documentation only documents the
|
||||
Armada XP SDRAM controller.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
|
||||
- reg: a resource specifier for the register space, which should
|
||||
include all SDRAM controller registers as per the datasheet.
|
||||
|
||||
Example:
|
||||
|
||||
sdramc@1400 {
|
||||
compatible = "marvell,armada-xp-sdram-controller";
|
||||
reg = <0x1400 0x500>;
|
||||
};
|
||||
@@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
The DDR controller of the AR7xxx and AR9xxx families provides an interface to
|
||||
flush the FIFO between various devices and the DDR. This is mainly used by
|
||||
the IRQ controller to flush the FIFO before running the interrupt handler of
|
||||
such devices.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: qca,ar9132-ddr-controller
|
||||
- const: qca,ar7240-ddr-controller
|
||||
- items:
|
||||
- enum:
|
||||
- qca,ar7100-ddr-controller
|
||||
- qca,ar7240-ddr-controller
|
||||
|
||||
"#qca,ddr-wb-channel-cells":
|
||||
description: |
|
||||
Specifies the number of cells needed to encode the write buffer channel
|
||||
index.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#qca,ddr-wb-channel-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ddr_ctrl: memory-controller@18000000 {
|
||||
compatible = "qca,ar9132-ddr-controller",
|
||||
"qca,ar7240-ddr-controller";
|
||||
reg = <0x18000000 0x100>;
|
||||
|
||||
#qca,ddr-wb-channel-cells = <1>;
|
||||
};
|
||||
|
||||
interrupt-controller {
|
||||
// ...
|
||||
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
|
||||
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
|
||||
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
|
||||
};
|
||||
@@ -1,12 +0,0 @@
|
||||
* H8/300 bus controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "renesas,h8300-bsc".
|
||||
- reg: Base address and length of BSC registers.
|
||||
|
||||
Example.
|
||||
bsc: memory-controller@fee01e {
|
||||
compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
|
||||
reg = <0xfee01e 8>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/renesas,h8300-bsc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: H8/300 bus controller
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Yoshinori Sato <ysato@users.sourceforge.jp>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,h8300h-bsc
|
||||
- renesas,h8s-bsc
|
||||
- const: renesas,h8300-bsc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
memory-controller@fee01e {
|
||||
compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
|
||||
reg = <0xfee01e 8>;
|
||||
};
|
||||
@@ -61,12 +61,23 @@ patternProperties:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- cfi-flash
|
||||
- jedec,spi-nor
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- power-domains
|
||||
- resets
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
@@ -0,0 +1,137 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: |
|
||||
Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
|
||||
Controller device
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Lukasz Luba <lukasz.luba@arm.com>
|
||||
|
||||
description: |
|
||||
The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
|
||||
DRAM memory chips are connected. The driver is to monitor the controller in
|
||||
runtime and switch frequency and voltage. To monitor the usage of the
|
||||
controller in runtime, the driver uses the PPMU (Platform Performance
|
||||
Monitoring Unit), which is able to measure the current load of the memory.
|
||||
When 'userspace' governor is used for the driver, an application is able to
|
||||
switch the DMC and memory frequency.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: samsung,exynos5422-dmc
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fout_spll
|
||||
- const: mout_sclk_spll
|
||||
- const: ff_dout_spll2
|
||||
- const: fout_bpll
|
||||
- const: mout_bpll
|
||||
- const: sclk_bpll
|
||||
- const: mout_mx_mspll_ccore
|
||||
- const: mout_mclk_cdrex
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
devfreq-events:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
description: phandles of the PPMU events used by the controller.
|
||||
|
||||
device-handle:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
phandle of the connected DRAM memory device. For more information please
|
||||
refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: DMC internal performance event counters in DREX0
|
||||
- description: DMC internal performance event counters in DREX1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: drex_0
|
||||
- const: drex_1
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: registers of DREX0
|
||||
- description: registers of DREX1
|
||||
|
||||
samsung,syscon-clk:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Phandle of the clock register set used by the controller, these registers
|
||||
are used for enabling a 'pause' feature and are not exposed by clock
|
||||
framework but they must be used in a safe way. The register offsets are
|
||||
in the driver code and specyfic for this SoC type.
|
||||
|
||||
vdd-supply: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clock-names
|
||||
- clocks
|
||||
- devfreq-events
|
||||
- device-handle
|
||||
- reg
|
||||
- samsung,syscon-clk
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5420.h>
|
||||
ppmu_dmc0_0: ppmu@10d00000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x10d00000 0x2000>;
|
||||
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
|
||||
clock-names = "ppmu";
|
||||
events {
|
||||
ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
|
||||
event-name = "ppmu-event3-dmc0_0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@10c20000 {
|
||||
compatible = "samsung,exynos5422-dmc";
|
||||
reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
|
||||
clocks = <&clock CLK_FOUT_SPLL>,
|
||||
<&clock CLK_MOUT_SCLK_SPLL>,
|
||||
<&clock CLK_FF_DOUT_SPLL2>,
|
||||
<&clock CLK_FOUT_BPLL>,
|
||||
<&clock CLK_MOUT_BPLL>,
|
||||
<&clock CLK_SCLK_BPLL>,
|
||||
<&clock CLK_MOUT_MX_MSPLL_CCORE>,
|
||||
<&clock CLK_MOUT_MCLK_CDREX>;
|
||||
clock-names = "fout_spll",
|
||||
"mout_sclk_spll",
|
||||
"ff_dout_spll2",
|
||||
"fout_bpll",
|
||||
"mout_bpll",
|
||||
"sclk_bpll",
|
||||
"mout_mx_mspll_ccore",
|
||||
"mout_mclk_cdrex";
|
||||
operating-points-v2 = <&dmc_opp_table>;
|
||||
devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
|
||||
<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
|
||||
device-handle = <&samsung_K3QF2F20DB>;
|
||||
vdd-supply = <&buck1_reg>;
|
||||
samsung,syscon-clk = <&clock>;
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <16 0>, <16 1>;
|
||||
interrupt-names = "drex_0", "drex_1";
|
||||
};
|
||||
@@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synopsys IntelliDDR Multi Protocol memory controller
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Manish Narani <manish.narani@xilinx.com>
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
|
||||
description: |
|
||||
The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
|
||||
32-bit bus width configurations.
|
||||
|
||||
The Zynq DDR ECC controller has an optional ECC support in half-bus width
|
||||
(16-bit) configuration.
|
||||
|
||||
These both ECC controllers correct single bit ECC errors and detect double bit
|
||||
ECC errors.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- xlnx,zynq-ddrc-a05
|
||||
- xlnx,zynqmp-ddrc-2.40a
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: xlnx,zynqmp-ddrc-2.40a
|
||||
then:
|
||||
required:
|
||||
- interrupts
|
||||
else:
|
||||
properties:
|
||||
interrupts: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
memory-controller@f8006000 {
|
||||
compatible = "xlnx,zynq-ddrc-a05";
|
||||
reg = <0xf8006000 0x1000>;
|
||||
};
|
||||
|
||||
- |
|
||||
axi {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
memory-controller@fd070000 {
|
||||
compatible = "xlnx,zynqmp-ddrc-2.40a";
|
||||
reg = <0x0 0xfd070000 0x0 0x30000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 112 4>;
|
||||
};
|
||||
};
|
||||
@@ -1,32 +0,0 @@
|
||||
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
|
||||
|
||||
The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
|
||||
bus width configurations.
|
||||
|
||||
The Zynq DDR ECC controller has an optional ECC support in half-bus width
|
||||
(16-bit) configuration.
|
||||
|
||||
These both ECC controllers correct single bit ECC errors and detect double bit
|
||||
ECC errors.
|
||||
|
||||
Required properties:
|
||||
- compatible: One of:
|
||||
- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
|
||||
- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
|
||||
- reg: Should contain DDR controller registers location and length.
|
||||
|
||||
Required properties for "xlnx,zynqmp-ddrc-2.40a":
|
||||
- interrupts: Property with a value describing the interrupt number.
|
||||
|
||||
Example:
|
||||
memory-controller@f8006000 {
|
||||
compatible = "xlnx,zynq-ddrc-a05";
|
||||
reg = <0xf8006000 0x1000>;
|
||||
};
|
||||
|
||||
mc: memory-controller@fd070000 {
|
||||
compatible = "xlnx,zynqmp-ddrc-2.40a";
|
||||
reg = <0x0 0xfd070000 0x0 0x30000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 112 4>;
|
||||
};
|
||||
@@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ti,da8xx-ddrctl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments da8xx DDR2/mDDR memory controller
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
Documentation:
|
||||
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,da850-ddr-controller
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
memory-controller@b0000000 {
|
||||
compatible = "ti,da850-ddr-controller";
|
||||
reg = <0xb0000000 0xe8>;
|
||||
};
|
||||
@@ -1,20 +0,0 @@
|
||||
* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller
|
||||
|
||||
The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features
|
||||
a set of registers which allow to tweak the controller's behavior.
|
||||
|
||||
Documentation:
|
||||
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "ti,da850-ddr-controller" - for da850 SoC based boards
|
||||
- reg: a tuple containing the base address of the memory
|
||||
controller and the size of the memory area to map
|
||||
|
||||
Example for da850 shown below.
|
||||
|
||||
ddrctl {
|
||||
compatible = "ti,da850-ddr-controller";
|
||||
reg = <0xb0000000 0xe8>;
|
||||
};
|
||||
@@ -11,9 +11,9 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,lp87565
|
||||
- const: ti,lp87565-q1
|
||||
enum:
|
||||
- ti,lp87565
|
||||
- ti,lp87565-q1
|
||||
|
||||
reg:
|
||||
description: I2C slave address
|
||||
|
||||
@@ -1,29 +0,0 @@
|
||||
EEPROMs (SPI) compatible with Microchip Technology 93xx46 family.
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
"atmel,at93c46"
|
||||
"atmel,at93c46d"
|
||||
"atmel,at93c56"
|
||||
"atmel,at93c66"
|
||||
"eeprom-93xx46"
|
||||
"microchip,93lc46b"
|
||||
- data-size : number of data bits per word (either 8 or 16)
|
||||
|
||||
Optional properties:
|
||||
- read-only : parameter-less property which disables writes to the EEPROM
|
||||
- select-gpios : if present, specifies the GPIO that will be asserted prior to
|
||||
each access to the EEPROM (e.g. for SPI bus multiplexing)
|
||||
|
||||
Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
apply. In particular, "reg" and "spi-max-frequency" properties must be given.
|
||||
|
||||
Example:
|
||||
eeprom@0 {
|
||||
compatible = "eeprom-93xx46";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cs-high;
|
||||
data-size = <8>;
|
||||
select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
70
Documentation/devicetree/bindings/misc/eeprom-93xx46.yaml
Normal file
70
Documentation/devicetree/bindings/misc/eeprom-93xx46.yaml
Normal file
@@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/misc/eeprom-93xx46.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip 93xx46 SPI compatible EEPROM family dt bindings
|
||||
|
||||
maintainers:
|
||||
- Cory Tusar <cory.tusar@pid1solutions.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- atmel,at93c46
|
||||
- atmel,at93c46d
|
||||
- atmel,at93c56
|
||||
- atmel,at93c66
|
||||
- eeprom-93xx46
|
||||
- microchip,93lc46b
|
||||
|
||||
data-size:
|
||||
description: number of data bits per word
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [8, 16]
|
||||
|
||||
reg:
|
||||
description: chip select of EEPROM
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency: true
|
||||
spi-cs-high: true
|
||||
|
||||
read-only:
|
||||
description:
|
||||
parameter-less property which disables writes to the EEPROM
|
||||
type: boolean
|
||||
|
||||
select-gpios:
|
||||
description:
|
||||
specifies the GPIO that needs to be asserted prior to each access
|
||||
of EEPROM (e.g. for SPI bus multiplexing)
|
||||
maxItems: 1
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- data-size
|
||||
- spi-max-frequency
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eeprom@0 {
|
||||
compatible = "eeprom-93xx46";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cs-high;
|
||||
data-size = <8>;
|
||||
select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
@@ -10,7 +10,7 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
|
||||
Required properties:
|
||||
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
|
||||
16-bit devices and so must be either 1 or 2 bytes.
|
||||
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
|
||||
- gpmc,cs-on-ns: Chip-select assertion time
|
||||
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
|
||||
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
|
||||
@@ -21,7 +21,7 @@ Required properties:
|
||||
- gpmc,access-ns: Start cycle to first data capture (read access)
|
||||
- gpmc,rd-cycle-ns: Total read cycle time
|
||||
- gpmc,wr-cycle-ns: Total write cycle time
|
||||
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
|
||||
- reg: Chip-select, base address (relative to chip-select)
|
||||
and size of NOR flash. Note that base address will be
|
||||
typically 0 as this is the start of the chip-select.
|
||||
|
||||
@@ -23,6 +23,7 @@ properties:
|
||||
- amd,s29gl256n
|
||||
- amd,s29gl512n
|
||||
- arm,versatile-flash
|
||||
- arm,vexpress-flash
|
||||
- cortina,gemini-flash
|
||||
- cypress,hyperflash
|
||||
- ge,imp3a-firmware-mirror
|
||||
|
||||
@@ -116,7 +116,6 @@ examples:
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
snps,tso;
|
||||
status = "okay";
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
|
||||
@@ -71,7 +71,6 @@ examples:
|
||||
ethernet@c8009000 {
|
||||
compatible = "intel,ixp4xx-ethernet";
|
||||
reg = <0xc8009000 0x1000>;
|
||||
status = "disabled";
|
||||
queue-rx = <&qmgr 4>;
|
||||
queue-txready = <&qmgr 21>;
|
||||
intel,npe-handle = <&npe 1>;
|
||||
@@ -82,7 +81,6 @@ examples:
|
||||
ethernet@c800c000 {
|
||||
compatible = "intel,ixp4xx-ethernet";
|
||||
reg = <0xc800c000 0x1000>;
|
||||
status = "disabled";
|
||||
queue-rx = <&qmgr 3>;
|
||||
queue-txready = <&qmgr 20>;
|
||||
intel,npe-handle = <&npe 2>;
|
||||
|
||||
96
Documentation/devicetree/bindings/net/micrel,ks8851.yaml
Normal file
96
Documentation/devicetree/bindings/net/micrel,ks8851.yaml
Normal file
@@ -0,0 +1,96 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/micrel,ks8851.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Micrel KS8851 Ethernet MAC (SPI and Parallel bus options)
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- micrel,ks8851 # SPI bus option
|
||||
- micrel,ks8851-mll # Parallel bus option
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: SPI or Parallel bus hardware address
|
||||
- description: Parallel bus command mode address
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The reset_n input pin
|
||||
|
||||
vdd-supply:
|
||||
description: |
|
||||
Analog 3.3V supply for Ethernet MAC
|
||||
|
||||
vdd-io-supply:
|
||||
description: |
|
||||
Digital 1.8V IO supply for Ethernet MAC
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- $ref: ethernet-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: micrel,ks8851
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: micrel,ks8851-mll
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/* SPI bus option */
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ethernet@0 {
|
||||
compatible = "micrel,ks8851";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <90 8>;
|
||||
vdd-supply = <&ext_l2>;
|
||||
vdd-io-supply = <&pm8921_lvs6>;
|
||||
reset-gpios = <&msmgpio 89 0>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
/* Parallel bus option */
|
||||
memory-controller {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ethernet@1,0 {
|
||||
compatible = "micrel,ks8851-mll";
|
||||
reg = <1 0x0 0x2>, <1 0x2 0x20000>;
|
||||
interrupt-parent = <&gpioc>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
@@ -1,18 +0,0 @@
|
||||
Micrel KS8851 Ethernet mac (MLL)
|
||||
|
||||
Required properties:
|
||||
- compatible = "micrel,ks8851-mll" of parallel interface
|
||||
- reg : 2 physical address and size of registers for data and command
|
||||
- interrupts : interrupt connection
|
||||
|
||||
Micrel KS8851 Ethernet mac (SPI)
|
||||
|
||||
Required properties:
|
||||
- compatible = "micrel,ks8851" or the deprecated "ks8851"
|
||||
- reg : chip select number
|
||||
- interrupts : interrupt connection
|
||||
|
||||
Optional properties:
|
||||
- vdd-supply: analog 3.3V supply for Ethernet mac
|
||||
- vdd-io-supply: digital 1.8V IO supply for Ethernet mac
|
||||
- reset-gpios: reset_n input pin
|
||||
@@ -67,7 +67,7 @@ Example:
|
||||
compatible = "ethernet-phy-id0007.0570";
|
||||
vsc8531,vddmac = <3300>;
|
||||
vsc8531,edge-slowdown = <7>;
|
||||
vsc8531,led-0-mode = <LINK_1000_ACTIVITY>;
|
||||
vsc8531,led-1-mode = <LINK_100_ACTIVITY>;
|
||||
vsc8531,led-0-mode = <VSC8531_LINK_1000_ACTIVITY>;
|
||||
vsc8531,led-1-mode = <VSC8531_LINK_100_ACTIVITY>;
|
||||
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
@@ -90,14 +90,11 @@ examples:
|
||||
# UART example on Raspberry Pi
|
||||
- |
|
||||
uart0 {
|
||||
status = "okay";
|
||||
|
||||
nfc {
|
||||
compatible = "samsung,s3fwrn82";
|
||||
|
||||
en-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
|
||||
wake-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -101,8 +101,6 @@ examples:
|
||||
|
||||
phy-mode = "gmii";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
@@ -148,32 +146,24 @@ examples:
|
||||
reg = <0x1>;
|
||||
phy-handle = <&phy_port0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
switch_port2: port@2 {
|
||||
reg = <0x2>;
|
||||
phy-handle = <&phy_port1>;
|
||||
phy-mode = "internal";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
switch_port3: port@3 {
|
||||
reg = <0x3>;
|
||||
phy-handle = <&phy_port2>;
|
||||
phy-mode = "internal";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
switch_port4: port@4 {
|
||||
reg = <0x4>;
|
||||
phy-handle = <&phy_port3>;
|
||||
phy-mode = "internal";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -183,34 +173,29 @@ examples:
|
||||
|
||||
interrupt-parent = <&switch10>;
|
||||
|
||||
phy_port0: phy@0 {
|
||||
phy_port0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
interrupts = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy_port1: phy@1 {
|
||||
phy_port1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
interrupts = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy_port2: phy@2 {
|
||||
phy_port2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
interrupts = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy_port3: phy@3 {
|
||||
phy_port3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
interrupts = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy_port4: phy@4 {
|
||||
phy_port4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
interrupts = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -17,10 +17,10 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: "realtek,rtl8723bs-bt"
|
||||
- const: "realtek,rtl8723cs-bt"
|
||||
- const: "realtek,rtl8822cs-bt"
|
||||
enum:
|
||||
- realtek,rtl8723bs-bt
|
||||
- realtek,rtl8723cs-bt
|
||||
- realtek,rtl8822cs-bt
|
||||
|
||||
device-wake-gpios:
|
||||
maxItems: 1
|
||||
|
||||
@@ -43,23 +43,20 @@ properties:
|
||||
- renesas,etheravb-r8a779a0 # R-Car V3U
|
||||
- const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-gbeth # RZ/G2{L,LC}
|
||||
- const: renesas,rzg2l-gbeth # RZ/G2L
|
||||
|
||||
reg: true
|
||||
|
||||
interrupts: true
|
||||
|
||||
interrupt-names: true
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: AVB functional clock
|
||||
- description: Optional TXC reference clock
|
||||
clocks: true
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: fck
|
||||
- const: refclk
|
||||
clock-names: true
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
@@ -145,14 +142,20 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,etheravb-rcar-gen2
|
||||
enum:
|
||||
- renesas,etheravb-rcar-gen2
|
||||
- renesas,rzg2l-gbeth
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mux
|
||||
- const: fil
|
||||
- const: arp_ns
|
||||
rx-internal-delay-ps: false
|
||||
else:
|
||||
properties:
|
||||
@@ -208,6 +211,36 @@ allOf:
|
||||
tx-internal-delay-ps:
|
||||
const: 2000
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,rzg2l-gbeth
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Main clock
|
||||
- description: Register access clock
|
||||
- description: Reference clock for RGMII
|
||||
clock-names:
|
||||
items:
|
||||
- const: axi
|
||||
- const: chi
|
||||
- const: refclk
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: AVB functional clock
|
||||
- description: Optional TXC reference clock
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: fck
|
||||
- const: refclk
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -53,10 +53,10 @@ properties:
|
||||
"#size-cells": true
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,am654-cpsw-nuss
|
||||
- const: ti,j721e-cpsw-nuss
|
||||
- const: ti,am642-cpsw-nuss
|
||||
enum:
|
||||
- ti,am654-cpsw-nuss
|
||||
- ti,j721e-cpsw-nuss
|
||||
- ti,am642-cpsw-nuss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -45,9 +45,9 @@ properties:
|
||||
pattern: "^cpts@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,am65-cpts
|
||||
- const: ti,j721e-cpts
|
||||
enum:
|
||||
- ti,am65-cpts
|
||||
- ti,j721e-cpts
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -40,7 +40,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-9a-f]+$":
|
||||
"@[0-9a-f]+(,[0-7])?$":
|
||||
type: object
|
||||
|
||||
properties:
|
||||
|
||||
@@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Socionext UniPhier eFuse bindings
|
||||
|
||||
maintainers:
|
||||
- Keiji Hayashibara <hayashibara.keiji@socionext.com>
|
||||
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "nvmem.yaml#"
|
||||
|
||||
properties:
|
||||
"#address-cells": true
|
||||
"#size-cells": true
|
||||
|
||||
compatible:
|
||||
const: socionext,uniphier-efuse
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// The UniPhier eFuse should be a subnode of a "soc-glue" node.
|
||||
|
||||
soc-glue@5f900000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x5f900000 0x2000>;
|
||||
|
||||
efuse@100 {
|
||||
compatible = "socionext,uniphier-efuse";
|
||||
reg = <0x100 0x28>;
|
||||
};
|
||||
|
||||
efuse@200 {
|
||||
compatible = "socionext,uniphier-efuse";
|
||||
reg = <0x200 0x68>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* Data cells */
|
||||
usb_rterm0: trim@54,4 {
|
||||
reg = <0x54 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm1: trim@55,4 {
|
||||
reg = <0x55 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm2: trim@58,4 {
|
||||
reg = <0x58 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm3: trim@59,4 {
|
||||
reg = <0x59 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_sel_t0: trim@54,0 {
|
||||
reg = <0x54 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t1: trim@55,0 {
|
||||
reg = <0x55 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t2: trim@58,0 {
|
||||
reg = <0x58 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t3: trim@59,0 {
|
||||
reg = <0x59 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i0: trim@56,0 {
|
||||
reg = <0x56 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i2: trim@5a,0 {
|
||||
reg = <0x5a 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user