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arm64: dts: qcom: sm6125: fix SDHCI CQE reg names

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[ Upstream commit 3de1172624b3c4ca65730bc34333ab493510b3e1 ]

SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
registers is cqhci, not core.

Fixes: cff4bbaf2a ("arm64: dts: qcom: Add support for SM6125")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Sony Xperia 10 II
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221026163646.37433-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2022-10-26 12:36:46 -04:00
committed by Greg Kroah-Hartman
parent 0f9ac04191
commit 75baeec464
1 changed files with 1 additions and 1 deletions
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arch/arm64/boot/dts/qcom/sm6125.dtsi
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@@ -408,7 +408,7 @@
sdhc_1: sdhci@4744000 { sdhc_1: sdhci@4744000 {
compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>; reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
reg-names = "hc", "core"; reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;