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UPSTREAM: dt-bindings: mmc: mtk-sd: Add hs400 dly3 setting

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Add hs400 dly3 setting for mtk-sd yaml

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210917124803.22871-2-wenbin.mei@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Bug: 234554003
Signed-off-by: Peng Zhou <Peng.Zhou@mediatek.com>
Change-Id: I2738b6774108d3dc8a12291f879744fb92c2d25b
(cherry picked from commit fb4708e6cb5c70a0dca5437640f1f85b9042256e)
This commit is contained in:
Wenbin Mei
2021-09-17 20:48:01 +08:00
committed by Carlos Llamas
parent 6551a55c4d
commit 9a63e4dcc0
1 changed files with 12 additions and 0 deletions
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12
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
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@@ -119,6 +119,18 @@ properties:
If present, HS400 command responses are sampled on rising edges. If present, HS400 command responses are sampled on rising edges.
If not present, HS400 command responses are sampled on falling edges. If not present, HS400 command responses are sampled on falling edges.
mediatek,hs400-ds-dly3:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Gear of the third delay line for DS for input data latch in data
pad macro, there are 32 stages from 0 to 31.
For different corner IC, the time is different about one step, it is
about 100ps.
The value is confirmed by doing scan and calibration to find a best
value with corner IC and it is valid only for HS400 mode.
minimum: 0
maximum: 31
mediatek,latch-ck: mediatek,latch-ck:
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
description: description: