Merge branch 'pci/hotplug'
- fix use-before-set error in ibmphp (Dan Carpenter)
- fix pciehp timeouts caused by Command Completed errata (Bjorn Helgaas)
- fix refcounting in pnv_php hotplug (Julia Lawall)
- clear pciehp Presence Detect and Data Link Layer Status Changed on
resume so we don't miss hotplug events (Mika Westerberg)
- only request pciehp control if we support it, so platform can use ACPI
hotplug otherwise (Mika Westerberg)
- convert SHPC to be builtin only (Mika Westerberg)
- request SHPC control via _OSC if we support it (Mika Westerberg)
- simplify SHPC handoff from firmware (Mika Westerberg)
* pci/hotplug:
PCI: Improve "partially hidden behind bridge" log message
PCI: Improve pci_scan_bridge() and pci_scan_bridge_extend() doc
PCI: Move resource distribution for single bridge outside loop
PCI: Account for all bridges on bus when distributing bus numbers
ACPI / hotplug / PCI: Drop unnecessary parentheses
ACPI / hotplug / PCI: Mark stale PCI devices disconnected
ACPI / hotplug / PCI: Don't scan bridges managed by native hotplug
PCI: hotplug: Add hotplug_is_native()
PCI: shpchp: Add shpchp_is_native()
PCI: shpchp: Fix AMD POGO identification
PCI: shpchp: Use dev_printk() for OSHP-related messages
PCI: shpchp: Remove get_hp_hw_control_from_firmware() wrapper
PCI: shpchp: Remove acpi_get_hp_hw_control_from_firmware() flags
PCI: shpchp: Rely on previous _OSC results
PCI: shpchp: Request SHPC control via _OSC when adding host bridge
PCI: shpchp: Convert SHPC to be builtin only
PCI: pciehp: Make pciehp_is_native() stricter
PCI: pciehp: Rename host->native_hotplug to host->native_pcie_hotplug
PCI: pciehp: Request control of native hotplug only if supported
PCI: pciehp: Clear Presence Detect and Data Link Layer Status Changed on resume
PCI: pnv_php: Add missing of_node_put()
PCI: pciehp: Add quirk for Command Completed errata
PCI: Add Qualcomm vendor ID
PCI: ibmphp: Fix use-before-set in get_max_bus_speed()
# Conflicts:
# drivers/acpi/pci_root.c
This commit is contained in:
@@ -407,6 +407,9 @@ struct pci_dev {
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struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
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#ifdef CONFIG_HOTPLUG_PCI_PCIE
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unsigned int broken_cmd_compl:1; /* No compl for some cmds */
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#endif
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#ifdef CONFIG_PCIE_PTM
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unsigned int ptm_root:1;
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unsigned int ptm_enabled:1;
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@@ -472,7 +475,8 @@ struct pci_host_bridge {
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unsigned int ignore_reset_delay:1; /* For entire hierarchy */
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unsigned int no_ext_tags:1; /* No Extended Tags */
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unsigned int native_aer:1; /* OS may use PCIe AER */
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unsigned int native_hotplug:1; /* OS may use PCIe hotplug */
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unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
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unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
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unsigned int native_pme:1; /* OS may use PCIe PME */
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unsigned int native_ltr:1; /* OS may use PCIe LTR */
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/* Resource alignment requirements */
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@@ -1451,8 +1455,10 @@ static inline int pci_irqd_intx_xlate(struct irq_domain *d,
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#ifdef CONFIG_PCIEPORTBUS
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extern bool pcie_ports_disabled;
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extern bool pcie_ports_native;
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#else
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#define pcie_ports_disabled true
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#define pcie_ports_native false
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#endif
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#ifdef CONFIG_PCIEASPM
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