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BACKPORT: arm64: errata: remove BF16 HWCAP due to incorrect result on Cortex-A510

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Cortex-A510's erratum #2658417 causes two BF16 instructions to return the
wrong result in rare circumstances when a pair of A510 CPUs are using
shared neon hardware.

The two instructions affected are BFMMLA and VMMLA, support for these is
indicated by the BF16 HWCAP. Remove it on affected platforms.

Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220909165938.3931307-4-james.morse@arm.com
[catalin.marinas@arm.com: add revision to the Kconfig help; remove .type]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Conflicts:
	arch/arm64/include/asm/sysreq.h

1. Added definition for ID_AA64ISAR1_EL1_BF16_MASK

Bug: 261510586
Change-Id: I83a5dd577fc8c0edd83c40b21f3fe54c54b6a9fa
(cherry picked from commit 1bdb0fbb2e27c51a6f311867726462c983a1d9ee)
Signed-off-by: Suren Baghdasaryan <surenb@google.com>
This commit is contained in:
James Morse
2022-09-09 17:59:38 +01:00
committed by Suren Baghdasaryan
parent 9563f49379
commit f794954635
5 changed files with 43 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/arm64/silicon-errata.rst
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@@ -102,6 +102,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 |
+----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_2658417 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |

13
arch/arm64/Kconfig
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@@ -711,6 +711,19 @@ config ARM64_ERRATUM_1508412
config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
bool bool
config ARM64_ERRATUM_2658417
bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
default y
help
This option adds the workaround for ARM Cortex-A510 erratum 2658417.
Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
BFMMLA or VMMLA instructions in rare circumstances when a pair of
A510 CPUs are using shared neon hardware. As the sharing is not
discoverable by the kernel, hide the BF16 HWCAP to indicate that
user-space should not be using these instructions.
If unsure, say Y.
config ARM64_ERRATUM_2119858 config ARM64_ERRATUM_2119858
bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
default y default y

1
arch/arm64/include/asm/sysreg.h
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@@ -778,6 +778,7 @@
#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 #define ID_AA64ISAR1_EL1_I8MM_SHIFT 52
#define ID_AA64ISAR1_EL1_DGH_SHIFT 48 #define ID_AA64ISAR1_EL1_DGH_SHIFT 48
#define ID_AA64ISAR1_EL1_BF16_SHIFT 44 #define ID_AA64ISAR1_EL1_BF16_SHIFT 44
#define ID_AA64ISAR1_EL1_BF16_MASK (0xfUL << ID_AA64ISAR1_EL1_BF16_SHIFT)
#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 #define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
#define ID_AA64ISAR1_EL1_SB_SHIFT 36 #define ID_AA64ISAR1_EL1_SB_SHIFT 36
#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 #define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32

26
arch/arm64/kernel/cpu_errata.c
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@@ -121,6 +121,22 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
} }
static DEFINE_RAW_SPINLOCK(reg_user_mask_modification);
static void __maybe_unused
cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused)
{
struct arm64_ftr_reg *regp;
regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1);
if (!regp)
return;
raw_spin_lock(&reg_user_mask_modification);
if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK)
regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;
raw_spin_unlock(&reg_user_mask_modification);
}
#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
.matches = is_affected_midr_range, \ .matches = is_affected_midr_range, \
.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
@@ -644,6 +660,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
CAP_MIDR_RANGE_LIST(broken_aarch32_aes), CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
}, },
#endif
#ifdef CONFIG_ARM64_ERRATUM_2658417
{
.desc = "ARM erratum 2658417",
.capability = ARM64_WORKAROUND_2658417,
/* Cortex-A510 r0p0 - r1p1 */
ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),
.cpu_enable = cpu_clear_bf16_from_user_emulation,
},
#endif #endif
{ {
} }

1
arch/arm64/tools/cpucaps
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@@ -63,6 +63,7 @@ WORKAROUND_1508412
WORKAROUND_1542419 WORKAROUND_1542419
WORKAROUND_1742098 WORKAROUND_1742098
WORKAROUND_2457168 WORKAROUND_2457168
WORKAROUND_2658417
WORKAROUND_TRBE_OVERWRITE_FILL_MODE WORKAROUND_TRBE_OVERWRITE_FILL_MODE
WORKAROUND_TSB_FLUSH_FAILURE WORKAROUND_TSB_FLUSH_FAILURE
WORKAROUND_TRBE_WRITE_OUT_OF_RANGE WORKAROUND_TRBE_WRITE_OUT_OF_RANGE