Pull MIPS updates from Ralf Baechle:
"Boston platform support:
- Document DT bindings
- Add CLK driver for board clocks
CM:
- Avoid per-core locking with CM3 & higher
- WARN on attempt to lock invalid VP, not BUG
CPS:
- Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6
- Prevent multi-core with dcache aliasing
- Handle cores not powering down more gracefully
- Handle spurious VP starts more gracefully
DSP:
- Add lwx & lhx missaligned access support
eBPF:
- Add MIPS support along with many supporting change to add the
required infrastructure
Generic arch code:
- Misc sysmips MIPS_ATOMIC_SET fixes
- Drop duplicate HAVE_SYSCALL_TRACEPOINTS
- Negate error syscall return in trace
- Correct forced syscall errors
- Traced negative syscalls should return -ENOSYS
- Allow samples/bpf/tracex5 to access syscall arguments for sane
traces
- Cleanup from old Kconfig options in defconfigs
- Fix PREF instruction usage by memcpy for MIPS R6
- Fix various special cases in the FPU eulation
- Fix some special cases in MIPS16e2 support
- Fix MIPS I ISA /proc/cpuinfo reporting
- Sort MIPS Kconfig alphabetically
- Fix minimum alignment requirement of IRQ stack as required by
ABI / GCC
- Fix special cases in the module loader
- Perform post-DMA cache flushes on systems with MAARs
- Probe the I6500 CPU
- Cleanup cmpxchg and add support for 1 and 2 byte operations
- Use queued read/write locks (qrwlock)
- Use queued spinlocks (qspinlock)
- Add CPU shared FTLB feature detection
- Handle tlbex-tlbp race condition
- Allow storing pgd in C0_CONTEXT for MIPSr6
- Use current_cpu_type() in m4kc_tlbp_war()
- Support Boston in the generic kernel
Generic platform:
- yamon-dt: Pull YAMON DT shim code out of SEAD-3 board
- yamon-dt: Support > 256MB of RAM
- yamon-dt: Use serial* rather than uart* aliases
- Abstract FDT fixup application
- Set RTC_ALWAYS_BCD to 0
- Add a MAINTAINERS entry
core kernel:
- qspinlock.c: include linux/prefetch.h
Loongson 3:
- Add support
Perf:
- Add I6500 support
SEAD-3:
- Remove GIC timer from DT
- Set interrupt-parent per-device, not at root node
- Fix GIC interrupt specifiers
SMP:
- Skip IPI setup if we only have a single CPU
VDSO:
- Make comment match reality
- Improvements to time code in VDSO"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits)
locking/qspinlock: Include linux/prefetch.h
MIPS: Fix MIPS I ISA /proc/cpuinfo reporting
MIPS: Fix minimum alignment requirement of IRQ stack
MIPS: generic: Support MIPS Boston development boards
MIPS: DTS: img: Don't attempt to build-in all .dtb files
clk: boston: Add a driver for MIPS Boston board clocks
dt-bindings: Document img,boston-clock binding
MIPS: Traced negative syscalls should return -ENOSYS
MIPS: Correct forced syscall errors
MIPS: Negate error syscall return in trace
MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select
MIPS16e2: Provide feature overrides for non-MIPS16 systems
MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo
MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions
MIPS: MIPS16e2: Identify ASE presence
MIPS: VDSO: Fix a mismatch between comment and preprocessor constant
MIPS: VDSO: Add implementation of gettimeofday() fallback
MIPS: VDSO: Add implementation of clock_gettime() fallback
MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse()
MIPS: Use current_cpu_type() in m4kc_tlbp_war()
...
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock
controller that derive all clocks from a single crystal, using some
documented and some undocumented PLLs, half dividers, counters and
gates. This is a best attempt to construct a clock driver for the
clocks so at least we can gate off unused hardware and driver the
PCI bus clock.
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[sboyd@codeaurora.org: Fix devm_ioremap_resource() return value
checking]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.
The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The goals are to:
- Allow precise control over and automatic selection of which
(sub)drivers are used for which SoC (which may change in the
future),
- Allow adding support for new SoCs easily,
- Allow compile-testing of all (sub)drivers,
- Keep driver selection logic in the subsystem-specific Kconfig,
independent from the architecture-specific Kconfig (i.e. no "select"
from arch/arm64/Kconfig.platforms), to avoid dependencies.
This is implemented by:
- Introducing Kconfig symbols for all drivers and sub-drivers,
- Introducing the Kconfig symbol CLK_RENESAS, which is enabled
automatically when building for a Renesas ARM platform, and which
enables all required drivers without interaction of the user, based
on SoC-specific ARCH_* symbols,
- Allowing the user to enable any Kconfig symbol manually if
COMPILE_TEST is enabled,
- Using the new Kconfig symbols instead of the ARCH_* symbols to
control compilation in the Makefile,
- Always entering drivers/clk/renesas/ during the build.
Note that currently not all (sub)drivers are enabled for
compile-testing, as they depend on independent fixes in other
subsystems.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The hi655x multi function device is a PMIC providing regulators.
The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement
this clock in order to add it in the hi655x MFD and allow proper wireless
initialization.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
[sboyd@codeaurora.org: Remove clkdev usage]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
chips have two clock inputs, XTAL or CLK, which are muxed into single
PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
while the 5P49V5923 requires external XTAL.
The PLL feeds two fractional dividers. Each fractional divider feeds
output mux, which allows selecting between clock from the fractional
divider itself or from output mux on output N-1. In case of output
mux 0, the output N-1 is instead connected to the output from the mux
feeding the PLL.
The driver thus far supports only the 5P49V5923 and 5P49V5933, while
it should be easily extensible to the whole 5P49V59xx family of chips
as they are all pretty similar.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Factor out the common functions into loongson1/clk.c
to support both Loongson1B and Loongson1C. And, put
the rest into loongson1/clk-loongson1b.c.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clock IP used on the Maxim PMICs max77686 and max77802 are
same. The configuration of clock register is also same except
the number of clocks.
Part of common code utilisation, there is 3 files for these chips
clock driver, one for common and two files for driver registration.
Combine both drivers into single file and move common code into
same common file reduces the 2 files and make max77686 and max77802
clock driver in single fine. This driver does not depends on the
parent driver structure. The regmap handle is acquired through
regmap APIs for the register access.
This combination of driver helps on adding clock driver for different
Maxim PMICs which has similar clock IP like MAX77620 and MAX20024.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Break the AmLogic clock code up so that only the necessary parts are
compiled and linked. The core code is selected by both arm and arm64
builds with COMMON_CLK_AMLOGIC. The individual drivers have their own
config options as well.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Pull clk updates from Stephen Boyd:
"It's the usual big pile of driver updates and additions, but we do
have a couple core changes in here as well.
Core:
- CLK_IS_CRITICAL support has been added. This should allow drivers
to properly express that a certain clk should stay on even if their
prepare/enable count drops to 0 (and in turn the parents of these
clks should stay enabled).
- A clk registration API has been added, clk_hw_register(), and an OF
clk provider API has been added, of_clk_add_hw_provider(). These
APIs have been put in place to further split clk providers from clk
consumers, with the goal being to have clk providers never deal
with struct clk pointers at all. Conversion of provider drivers is
on going. clkdev has also gained support for registering clk_hw
pointers directly so we can convert drivers that don't use
devicetree.
New Drivers:
- Marvell ap806 and cp110 system controllers (with clks inside!)
- Hisilicon Hi3519 clock and reset controller
- Axis ARTPEC-6 clock controllers
- Oxford Semiconductor OXNAS clock controllers
- AXS10X I2S PLL
- Rockchip RK3399 clock and reset controller
Updates:
- MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos
542x SoCs, and some more clk ID exporting for bus frequency scaling
- Proper BCM2835 PCM clk support and various other clks
- i.MX clk updates for i.MX6SX, i.MX7, and VF610
- Renesas updates for R-Car H3
- Tegra210 got updates for DisplayPort and HDMI 2.0
- Rockchip driver refactorings and fixes due to adding RK3399 support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits)
clk: fix critical clock locking
clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM
clk: ingenic: Allow divider value to be divided
clk: sunxi: Add display and TCON0 clocks driver
clk: rockchip: drop old_rate calculation on pll rate changes
clk: rockchip: simplify GRF handling in pll clocks
clk: rockchip: lookup General Register Files in rockchip_clk_init
clk: rockchip: fix the rk3399 sdmmc sample / drv name
clk: mvebu: new driver for Armada CP110 system controller
dt-bindings: arm: add DT binding for Marvell CP110 system controller
clk: mvebu: new driver for Armada AP806 system controller
clk: hisilicon: add CRG driver for hi3519 soc
clk: hisilicon: export some hisilicon APIs to modules
reset: hisilicon: add reset controller driver for hisilicon SOCs
clk: bcm/kona: Do not use sizeof on pointer type
clk: qcom: msm8916: Fix crypto clock flags
clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
clk/axs10x: Add I2S PLL clock driver
clk: imx7d: fix ahb clock mux 1
clk: fix comment of devm_clk_hw_register()
...
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch has the goal of adding a clock driver
that programs this PLL.
At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Reformatted driver structure and of match]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The drivers/clk/mvebu directory is only being built when
CONFIG_PLAT_ORION=y. As we are going to support additional mvebu
platforms in drivers/clk/mvebu, which don't have CONFIG_PLAT_ORION=y,
we need to recurse into this directory regardless of the value of
CONFIG_PLAT_ORION.
Since all files in drivers/clk/mvebu/ are already conditionally
compiled depending on various Kconfig options, we can recurse
unconditionally into drivers/clk/mvebu without any other change.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Along with the above mentioned Kconfig changes it seems appropriate
to also rename directories that only hold drivers for such SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The arch independent drivers can be build testeed with
COMPILE_TEST. Let's allow that for drivers/clk/ti.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
As of 9b5ba0df4e ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms
that use Renesas clock drivers now select ARCH_RENESAS. As it is present in
drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The change adds COMMON_CLK_NXP configuration symbol and enables it for
NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp
folder for NXP common clock framework drivers other than LPC18XX one.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Add a new R-Car H3 Clock Pulse Generator / Module Standby and Software
Reset driver, using the new CPG/MSSR driver core.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Provide support for Sigma Designs Tango4 clock generator.
NOTE: This driver is incompatible with Tango3 clkgen.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[sboyd@codeaurora.org: Add kernel.h include for panic/sprintf]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull ARM SoC driver updates from Olof Johansson:
"As we've enabled multiplatform kernels on ARM, and greatly done away
with the contents under arch/arm/mach-*, there's still need for
SoC-related drivers to go somewhere.
Many of them go in through other driver trees, but we still have
drivers/soc to hold some of the "doesn't fit anywhere" lowlevel code
that might be shared between ARM and ARM64 (or just in general makes
sense to not have under the architecture directory).
This branch contains mostly such code:
- Drivers for qualcomm SoCs for SMEM, SMD and SMD-RPM, used to
communicate with power management blocks on these SoCs for use by
clock, regulator and bus frequency drivers.
- Allwinner Reduced Serial Bus driver, again used to communicate with
PMICs.
- Drivers for ARM's SCPI (System Control Processor). Not to be
confused with PSCI (Power State Coordination Interface). SCPI is
used to communicate with the assistant embedded cores doing power
management, and we have yet to see how many of them will implement
this for their hardware vs abstracting in other ways (or not at all
like in the past).
- To make confusion between SCPI and PSCI more likely, this release
also includes an update of PSCI to interface version 1.0.
- Rockchip support for power domains.
- A driver to talk to the firmware on Raspberry Pi"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (57 commits)
soc: qcom: smd-rpm: Correct size of outgoing message
bus: sunxi-rsb: Add driver for Allwinner Reduced Serial Bus
bus: sunxi-rsb: Add Allwinner Reduced Serial Bus (RSB) controller bindings
ARM: bcm2835: add mutual inclusion protection
drivers: psci: make PSCI 1.0 functions initialization version dependent
dt-bindings: Correct paths in Rockchip power domains binding document
soc: rockchip: power-domain: don't try to print the clock name in error case
soc: qcom/smem: add HWSPINLOCK dependency
clk: berlin: add cpuclk
ARM: berlin: dts: add CLKID_CPU for BG2Q
ARM: bcm2835: Add the Raspberry Pi firmware driver
soc: qcom: smem: Move RPM message ram out of smem DT node
soc: qcom: smd-rpm: Correct the active vs sleep state flagging
soc: qcom: smd: delete unneeded of_node_put
firmware: qcom-scm: build for correct architecture level
soc: qcom: smd: Correct SMEM items for upper channels
qcom-scm: add missing prototype for qcom_scm_is_available()
qcom-scm: fix endianess issue in __qcom_scm_is_call_available
soc: qcom: smd: Reject send of too big packets
soc: qcom: smd: Handle big endian CPUs
...
* clk-iproc:
clk: iproc: define Broadcom NS2 iProc clock binding
clk: iproc: define Broadcom NSP iProc clock binding
clk: ns2: add clock support for Broadcom Northstar 2 SoC
clk: iproc: Separate status and control variables
clk: iproc: Split off dig_filter
clk: iproc: Add PLL base write function
clk: nsp: add clock support for Broadcom Northstar Plus SoC
clk: iproc: Add PWRCTRL support
clk: cygnus: Convert all macros to all caps
ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
The Broadcom Northstar 2 SoC is architected under the iProc
architecture. It has the following PLLs: GENPLL SCR, GENPLL SW,
LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull Allwinner clock additions for 4.4 from Maxime Ripard:
- Support for the Audio PLL and child clocks
- Support for the A33 AHB gates
- New clk-multiplier generic driver
* tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi: mod1 clock support
clk: sunxi: codec clock support
clk: sunxi: pll2: Add A13 support
clk: sunxi: Add a driver for the PLL2
clk: Add a basic multiplier clock
clk: sunxi: Add A33 gates support
Some clocks are using a multiplier component, however, unlike their mux,
gate or divider counterpart, these factors don't have a basic clock
implementation.
This leads to code duplication across platforms that want to use that kind
of clocks, and the impossibility to use the composite clocks with such a
clock without defining your own rate operations.
Create such a driver in order to remove these issues, and hopefully factor
the implementations, reducing code size across platforms and consolidating
the various implementations.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
* clk-bcm2835:
clk: bcm2835: Add support for programming the audio domain clocks
clk: bcm2835: Add binding docs for the new platform clock driver.
clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Drop clk.h include, remove some casts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
drivers are going in there so let's follow them.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Power Interface(SCPI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.
This patch adds support for the clocks provided by SCP using SCPI
protocol.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org
The file clk-gpio-gate.c does not only contain the gate clock, but also
the mux clock. Rename the file to clk-gpio.c.
Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull clock framework updates from Michael Turquette:
"The changes to the common clock framework for 4.2 are dominated by new
drivers and updates to existing ones, as usual.
There are some fixes to the framework itself and several cleanups for
sparse warnings, etc"
* tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
clk: stm32: Add clock driver for STM32F4[23]xxx devices
dt-bindings: Document the STM32F4 clock bindings
cpufreq: exynos: remove Exynos4210 specific cpufreq driver support
ARM: Exynos: switch to using generic cpufreq driver for Exynos4210
clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock
clk: samsung: add infrastructure to register cpu clocks
clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support
doc: dt: add documentation for lpc1850-ccu clk driver
clk: add lpc18xx ccu clk driver
doc: dt: add documentation for lpc1850-cgu clk driver
clk: add lpc18xx cgu clk driver
clk: keystone: add support for post divider register for main pll
clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSED
clk: cygnus: remove Cygnus dummy clock binding
clk: cygnus: add clock support for Broadcom Cygnus
clk: Change bcm clocks build dependency
clk: iproc: add initial common clock support
clk: iproc: define Broadcom iProc clock binding
MAINTAINERS: update email for Michael Turquette
clk: meson: add some error handling in meson_clk_register_cpu()
...
Pull MIPS updates from Ralf Baechle:
- Improvements to the tlb_dump code
- KVM fixes
- Add support for appended DTB
- Minor improvements to the R12000 support
- Minor improvements to the R12000 support
- Various platform improvments for BCM47xx
- The usual pile of minor cleanups
- A number of BPF fixes and improvments
- Some improvments to the support for R3000 and DECstations
- Some improvments to the ATH79 platform support
- A major patchset for the JZ4740 SOC adding support for the CI20 platform
- Add support for the Pistachio SOC
- Minor BMIPS/BCM63xx platform support improvments.
- Avoid "SYNC 0" as memory barrier when unlocking spinlocks
- Add support for the XWR-1750 board.
- Paul's __cpuinit/__cpuinitdata cleanups.
- New Malta CPU board support large memory so enable ZONE_DMA32.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits)
MIPS: spinlock: Adjust arch_spin_lock back-off time
MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA
MIPS: BCM47xx: Simplify handling SPROM revisions
MIPS: Cobalt Don't use module_init in non-modular MTD registration.
MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/
MIPS: use for_each_sg()
MIPS: BCM47xx: Don't select BCMA_HOST_PCI
MIPS: BCM47xx: Add helper variable for storing NVRAM length
MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
MIPS: Replace smp_mb with release barrier function in unlocks.
MIPS: i8259: DT support
MIPS: Malta: Basic DT plumbing
MIPS: include errno.h for ENODEV in mips-cm.h
MIPS: Define GCR_GIC_STATUS register fields
MIPS: BPF: Introduce BPF ASM helpers
MIPS: BPF: Use BPF register names to describe the ABI
MIPS: BPF: Move register definition to the BPF header
MIPS: net: BPF: Replace RSIZE with SZREG
MIPS: BPF: Free up some callee-saved registers
MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
...
Pull ARM SoC platform support updates from Kevin Hilman:
"Our SoC branch usually contains expanded support for new SoCs and
other core platform code. Some highlights from this round:
- sunxi: SMP support for A23 SoC
- socpga: big-endian support
- pxa: conversion to common clock framework
- bcm: SMP support for BCM63138
- imx: support new I.MX7D SoC
- zte: basic support for ZX296702 SoC"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
ARM: zx: Add basic defconfig support for ZX296702
ARM: dts: zx: add an initial zx296702 dts and doc
clk: zx: add clock support to zx296702
dt-bindings: Add #defines for ZTE ZX296702 clocks
ARM: socfpga: fix build error due to secondary_startup
MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
ARM: ep93xx: simone: support for SPI-based MMC/SD cards
MAINTAINERS: update Shawn's email to use kernel.org one
ARM: socfpga: support suspend to ram
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
ARM: EXYNOS: register power domain driver from core_initcall
ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
ARM: SAMSUNG: Constify platform_device_id
ARM: EXYNOS: Constify irq_domain_ops
ARM: EXYNOS: add coupled cpuidle support for Exynos3250
ARM: EXYNOS: add exynos_get_boot_addr() helper
ARM: EXYNOS: add exynos_set_boot_addr() helper
ARM: EXYNOS: make exynos_core_restart() less verbose
ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
...
The driver supports decoding and statically modelling PLL state (i.e.
we inherit state from bootloader) and provides support for all
peripherals that support simple one-bit gated clocks. The covers all
peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested on an STM32F429I-Discovery board. The clock counts
for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
looks OK when checked with a stopwatch. I have also tested a prototype
driver for the RNG hardware. The RNG clock is correctly enabled by the
framework (also did inverse test and proved that by changing DT to
configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
[sboyd@codeaurora.org: Silence sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
