[ Upstream commit 58922910add18583d5273c2edcdb9fd7bf4eca02 ]
The display pixel clock has a requirement on certain newer platforms to
support M/N as (2/3) and the final D value calculated results in
underflow errors.
As the current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.
Fixes: 99cbd064b0 ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit b77d8306d84f83d1da68028a68c91da9c867b6f6 ]
Use floor ops on SDCC1 APPS clock in order to round down selected clock
frequency and avoid overclocking SD/eMMC cards.
For example, currently HS200 cards were failling tuning as they were
actually being clocked at 384MHz instead of 192MHz.
This caused some boards to disable 1.8V I/O and force the eMMC into the
standard HS mode (50MHz) and that appeared to work despite the eMMC being
overclocked to 96Mhz in that case.
There was a previous commit to use floor ops on SDCC clocks, but it looks
to have only covered SDCC2 clock.
Fixes: 9607f6224b ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks")
Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220210173100.505128-1-robimarko@gmail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 6e6fec3f961c00ca34ffb4bf2ad9febb4b499f8d ]
On SC7180 we observe black screens because the gdsc is being
enabled/disabled very rapidly and the GDSC FSM state does not work as
expected. This is due to the fact that the GDSC reset value is being
updated from SW.
The recommended transition delay for mdss core gdsc updated for
SC7180/SC7280/SM8250.
Fixes: dd3d066221 ("clk: qcom: Add display clock controller driver for SC7180")
Fixes: 1a00c962f9 ("clk: qcom: Add display clock controller driver for SC7280")
Fixes: 80a18f4a85 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/20220223185606.3941-2-tdas@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sboyd@kernel.org: lowercase hex]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 4e7c4d3652f96f41179aab3ff53025c7a550d689 ]
GDSCs have multiple transition delays which are used for the GDSC FSM
states. Older targets/designs required these values to be updated from
gdsc code to certain default values for the FSM state to work as
expected. But on the newer targets/designs the values updated from the
GDSC driver can hamper the FSM state to not work as expected.
On SC7180 we observe black screens because the gdsc is being
enabled/disabled very rapidly and the GDSC FSM state does not work as
expected. This is due to the fact that the GDSC reset value is being
updated from SW.
Thus add support to update the transition delay from the clock
controller gdscs as required.
Fixes: 45dd0e5531 ("clk: qcom: Add support for GDSCs)
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/20220223185606.3941-1-tdas@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
commit a1f0019c342bd83240b05be68c9888549dde7935 upstream.
In the event that the bootloader has configured the Trion PLL as source
for the display clocks, e.g. for the continuous splashscreen, then there
will also be RCGs that are clocked by this instance.
Reconfiguring, and in particular disabling the output of, the PLL will
cause issues for these downstream RCGs and has been shown to prevent
them from being re-parented.
Follow downstream and skip configuration if it's determined that the PLL
is already running.
Fixes: 59128c20a6 ("clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20211123162508.153711-1-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 9a61f813fcc8d56d85fcf9ca6119cf2b5ac91dd5 upstream.
The function mux_get_parent() uses qcom_find_src_index() to find the
parent clock index, which is incorrect: qcom_find_src_index() uses src
enum for the lookup, while mux_get_parent() should use cfg field (which
corresponds to the register value). Add qcom_find_cfg_index() function
doing this kind of lookup and use it for mux parent lookup.
Fixes: df96401649 ("clk: qcom: add parent map for regmap mux")
Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20211115233407.1046179-1-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 05cf3ec00d460b50088d421fb878a0f83f57e262 ]
The gcc_aggre1_pnoc_ahb_clk is crucial for the proper MSM8996/APQ8096
functioning. If it gets disabled, several subsytems will stop working
(including eMMC/SDCC and USB). There are no in-kernel users of this
clock, so it is much simpler to remove from the kernel.
The clock was first removed in the commit 9e60de1cf2 ("clk: qcom:
Remove gcc_aggre1_pnoc_ahb_clk from msm8996") by Stephen Boyd, but got
added back in the commit b567752144 ("clk: qcom: Add some missing gcc
clks for msm8996") by Rajendra Nayak.
Let's remove it again in hope that nobody adds it back.
Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Fixes: b567752144 ("clk: qcom: Add some missing gcc clks for msm8996")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20211104011155.2209654-1-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Pull clk fix from Stephen Boyd:
"One patch to fix an unused variable warning in a Qualcomm clk driver"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-sm6350: Remove unused variable
Pull clk updates from Stephen Boyd:
"Nothing changed in the clk framework core this time around. We did get
some updates to the basic clk types to use determine_rate for the
divider type and add a power of two fractional divider flag though.
Otherwise, this is a collection of clk driver updates. More than half
the diffstat is in the Qualcomm clk driver where we add a bunch of
data to describe clks on various SoCs and fix bugs. The other big new
thing in here is the Mediatek MT8192 clk driver. That's been under
review for a while and it's nice to see that it's finally upstream.
Beyond that it's the usual set of minor fixes and tweaks to clk
drivers. There are some non-clk driver bits in here which have all
been acked by the respective maintainers.
New Drivers:
- Support video, gpu, display clks on qcom sc7280 SoCs
- GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
- Multimedia clks (MMCC) on qcom MSM8994/MSM8992
- RPMh clks on qcom SM6350 SoCs
- Support for Mediatek MT8192 SoCs
- Add display (DU and DSI) clocks on Renesas R-Car V3U
- Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
resets on Renesas RZ/G2L
Updates:
- Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
- Add power of two flag to fractional divider clk type
- Migrate some clk drivers to clk_divider_ops.determine_rate
- Migrate to clk_parent_data in gcc-sdm660
- Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
- Switch from .round_rate to .determine_rate in clk-divider-gate
- Fix clock tree update for TF-A controlled clocks for all i.MX8M
- Add missing M7 core clock for i.MX8MN
- YAML conversion of rk3399 clock controller binding
- Removal of GRF dependency for the rk3328/rk3036 pll types
- Drop CLK_IS_CRITICAL flag from Tegra fuse clk
- Make CLK_R9A06G032 Kconfig symbol invisible
- Convert various DT bindings to YAML"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
dt-bindings: clock: samsung: fix header path in example
clk: tegra: fix old-style declaration
clk: qcom: Add SM6350 GCC driver
MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
dt-bindings: clock: samsung: convert Exynos4 to dtschema
dt-bindings: clock: samsung: convert Exynos3250 to dtschema
dt-bindings: clock: samsung: convert Exynos542x to dtschema
dt-bindings: clock: samsung: add bindings for Exynos external clock
dt-bindings: clock: samsung: convert Exynos5250 to dtschema
clk: vc5: Add properties for configuring SD/OE behavior
clk: vc5: Use dev_err_probe
dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
clk: zynqmp: Fix kernel-doc format
clk: at91: clk-generated: Limit the requested rate to our range
clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
clk: zynqmp: Fix a memory leak
clk: zynqmp: Check the return type
...
Commit 5658e8cf1a ("clk: qcom: add video clock controller driver for
SM8150") and commit 0e94711a1f ("clk: qcom: add video clock controller
driver for SM8250") add config SM_VIDEOCC_8150 and config SM_VIDEOCC_8250,
which select the non-existing configs SDM_GCC_8150 and SDM_GCC_8250,
respectively.
Hence, ./scripts/checkkconfigsymbols.py warns:
SDM_GCC_8150
Referencing files: drivers/clk/qcom/Kconfig
SDM_GCC_8250
Referencing files: drivers/clk/qcom/Kconfig
It is probably just a typo (or naming confusion of using SM_GCC_xxx and
SDM_GCC_xxx for various Qualcomm clock drivers) in the config definitions
for config SM_VIDEOCC_8150 and SM_VIDEOCC_8250, and intends to select the
existing SM_GCC_8150 and SM_GCC_8250, respectively.
Adjust the selects to the existing configs.
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210816135930.11810-1-lukas.bulwahn@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Using parent_data and parent_hws, instead of parent_names, does protect
against some cases of incompletely defined clock trees. While it turns
out that the bug being chased this time was totally unrelated, this
patch converts the SDM660 GCC driver to avoid such issues.
The "xo" fixed_factor clock is unused within the gcc driver, but
referenced from the DSI PHY. So it's left in place until the DSI driver
is updated.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org
[sboyd@kernel.org: Reduce diff by moving enum and tables back to
original position in previous patch]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In the next patch we're going to change these tables to reference the
PLL structures directly. Let's move them here so the diff is easier to
read. No functional change in this patch.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
MSM8939 has 3 a53pll clocks with different frequency table for Cluster0,
Cluster1 and CCI. It adds function qcom_a53pll_get_freq_tbl() to create
pll_freq_tbl from OPP, so that those a53pll frequencies can be defined
in DT with operating-points-v2 bindings rather than being coded in the
driver. In this case, one compatible rather than three would be needed
for these 3 a53pll clocks.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-5-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Different from MSM8916 which has only one a53pll/mux clock, MSM8939 gets
three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache
Coherent Interconnect). That said, a53pll/mux clock needs to be named
uniquely. Append @unit-address of device node to the clock name, so
that a53pll/mux will be named like below on MSM8939.
a53pll@b016000
a53pll@b116000
a53pll@b1d0000
a53mux@b1d1000
a53mux@b011000
a53mux@b111000
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-3-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clock source for MSM8916 cpu cores is like below.
|\
a53pll --------| \ a53mux +------+
| |------------| cpus |
gpll0_vote --------| / +------+
|/
So a53mux rather than a53pll is actually the parent clock of cpu cores.
It makes more sense to flag a53mux as critical instead, so that when
either a53pll or gpll0_vote is used by cpu cores, the clock will be kept
enabled while the other can be disabled.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-2-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As GDSCs are registered and found to be already enabled gdsc_init()
ensures that 1) the kernel state matches the hardware state, and 2)
votable GDSCs are properly enabled from this master as well.
But as the (optional) supply regulator is enabled deep into
gdsc_toggle_logic(), which is only executed for votable GDSCs, the
kernel's state of the regulator might not match the hardware. The
regulator might be automatically turned off if no other users are
present or the next call to gdsc_disable() would cause an unbalanced
regulator_disable().
Given that the votable case deals with an already enabled GDSC, most of
gdsc_enable() and gdsc_toggle_logic() can be skipped. Reduce it to just
clearing the SW_COLLAPSE_MASK and enabling hardware control to simply
call regulator_enable() in both cases.
The enablement of hardware control seems to be an independent property
from the GDSC being enabled, so this is moved outside that conditional
segment.
Lastly, as the propagation of ALWAYS_ON to GENPD_FLAG_ALWAYS_ON needs to
happen regardless of the initial state this is grouped together with the
other sc->pd updates at the end of the function.
Cc: stable@vger.kernel.org
Fixes: 37416e5549 ("clk: qcom: gdsc: Handle GDSC regulator supplies")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721224056.3035016-1-bjorn.andersson@linaro.org
[sboyd@kernel.org: Rephrase commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Fix gcc '-Wunused-const-variable' warnings:
drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined
but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map'
defined but not used [-Wunused-const-variable=]
Let's remove them.
Signed-off-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/r/20210609061848.87415-1-pulehui@huawei.com
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
