0855054fa8
[ Upstream commit b289cdecc7c3e25e001cde260c882e4d9a8b0772 ]
As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be
1600 MHz, but with current multiplier and divider values this resulted
to 1596 MHz.
This patch updates the multiplier and divider values for PLL2 and PLL3
so that we get the exact (1600 MHz) values.
Fixes: 17f0ff3d49 ("clk: renesas: Add support for R9A07G044 SoC")
Suggested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
213 lines
6.8 KiB
C
213 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G2L CPG driver
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include "rzg2l-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_OSC_DIV1000,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV16,
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CLK_PLL2_DIV20,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV2_4,
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CLK_PLL3_DIV2_4_2,
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CLK_PLL3_DIV4,
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CLK_PLL4,
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CLK_PLL5,
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CLK_PLL5_DIV2,
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CLK_PLL6,
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CLK_P1_DIV2,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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/* Divider tables */
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static const struct clk_div_table dtable_1_32[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{4, 32},
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{0, 0},
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};
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static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
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DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
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DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
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/* Core output clk */
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DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
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DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
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dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
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DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
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DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
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DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
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DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
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DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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};
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static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
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DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
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0x514, 0),
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DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
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0x518, 0),
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DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
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0x518, 1),
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DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
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0x52c, 0),
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DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
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0x52c, 1),
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DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
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0x570, 0),
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DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
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0x570, 1),
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DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
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0x570, 2),
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DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
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0x570, 3),
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DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
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0x570, 4),
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DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
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0x570, 5),
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DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
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0x570, 6),
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DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
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0x570, 7),
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DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
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0x578, 0),
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DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
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0x578, 1),
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DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
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0x578, 2),
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DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
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0x578, 3),
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DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
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0x580, 0),
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DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
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0x580, 1),
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DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
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0x580, 2),
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DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
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0x580, 3),
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DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 0),
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DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 1),
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DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 2),
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DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 3),
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DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 4),
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DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
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0x588, 0),
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DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
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0x594, 0),
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DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
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0x598, 0),
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DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
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0x5a8, 0),
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DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
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0x5a8, 1),
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};
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static struct rzg2l_reset r9a07g044_resets[] = {
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DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
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DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
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DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
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DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
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DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
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DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
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DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
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DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
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DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
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DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
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DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
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DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
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DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
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DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
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DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
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DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
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DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
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DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
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DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
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DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
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DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
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DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
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DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
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DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
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DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
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DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
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DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
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DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
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DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
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DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
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};
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static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
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MOD_CLK_BASE + R9A07G044_IA55_CLK,
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MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
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};
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const struct rzg2l_cpg_info r9a07g044_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a07g044_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Critical Module Clocks */
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.crit_mod_clks = r9a07g044_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
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/* Module Clocks */
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.mod_clks = r9a07g044_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
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.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
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/* Resets */
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.resets = r9a07g044_resets,
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.num_resets = ARRAY_SIZE(r9a07g044_resets),
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};
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