Marc Zyngier f4a81f5a85 irqchip/gic-v4.1: Allow direct invalidation of VLPIs ...

Just like for INVALL, GICv4.1 has grown a VPE-aware INVLPI register.
Let's plumb it in and make use of the DirectLPI code in that case.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Link: https://lore.kernel.org/r/20191224111055.11836-16-maz@kernel.org

2020-01-22 14:22:21 +00:00

..

arm-gic-common.h

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2019-07-08 11:01:13 -07:00

arm-gic-v3.h

irqchip/gic-v4.1: Allow direct invalidation of VLPIs

2020-01-22 14:22:21 +00:00

arm-gic-v4.h

irqchip/gic-v4.1: Add VPE residency callback

2020-01-22 14:22:20 +00:00

arm-gic.h

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2019-07-08 11:01:13 -07:00

arm-vic.h

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chained_irq.h

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irq-bcm2836.h

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irq-davinci-aintc.h

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irq-davinci-cp-intc.h

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irq-ixp4xx.h

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irq-madera.h

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irq-omap-intc.h

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irq-partition-percpu.h

irqchip: Add include guard to irq-partition-percpu.h

2019-08-20 10:35:46 +01:00

irq-sa11x0.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19 17:09:55 +02:00

mmp.h

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mxs.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19 17:09:55 +02:00

versatile-fpga.h

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xtensa-mx.h

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xtensa-pic.h

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