17790ef9ad
[ Upstream commit 33826e9c6ba76b265d4e26cb95493fa27ed78974 ]
Block at <ff800400 0x4c> is a TWD that contains timers, watchdog and
reset. Actual timers happen to be at block beginning but they only span
across the first 0x28 registers. It means the old block description was
incorrect (size 0x3c).
Drop timers binding for now and use documented TWD binding. Timers
should be properly documented and defined as TWD subnode.
Fixes: 2961f69f15 ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
338 lines
6.8 KiB
Plaintext
338 lines
6.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/soc/bcm-pmb.h>
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/dts-v1/;
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x0>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0xfff8>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0xfff8>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0xfff8>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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axi@81000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x81000000 0x4000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x2000 0x2000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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clocks {
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periph_clk: periph_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "periph";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x80000000 0x281000>;
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enet: ethernet@2000 {
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compatible = "brcm,bcm4908-enet";
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reg = <0x2000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "rx", "tx";
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};
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usb_phy: usb-phy@c200 {
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compatible = "brcm,bcm4908-usb-phy";
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reg = <0xc200 0x100>;
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reg-names = "ctrl";
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power-domains = <&pmb BCM_PMB_HOST_USB>;
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dr_mode = "host";
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brcm,has-xhci;
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brcm,has-eohci;
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#phy-cells = <1>;
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status = "disabled";
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};
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ehci: usb@c300 {
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compatible = "generic-ehci";
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reg = <0xc300 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb_phy PHY_TYPE_USB2>;
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status = "disabled";
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};
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ohci: usb@c400 {
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compatible = "generic-ohci";
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reg = <0xc400 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb_phy PHY_TYPE_USB2>;
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status = "disabled";
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};
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xhci: usb@d000 {
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compatible = "generic-xhci";
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reg = <0xd000 0x8c8>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb_phy PHY_TYPE_USB3>;
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status = "disabled";
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};
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bus@80000 {
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compatible = "simple-bus";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0 0x80000 0x50000>;
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ethernet-switch@0 {
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compatible = "brcm,bcm4908-switch";
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reg = <0x0 0x40000>,
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<0x40000 0x110>,
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<0x40340 0x30>,
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<0x40380 0x30>,
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<0x40600 0x34>,
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<0x40800 0x208>;
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reg-names = "core", "reg", "intrl2_0",
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"intrl2_1", "fcb", "acb";
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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brcm,num-gphy = <5>;
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brcm,num-rgmii-ports = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phy-mode = "internal";
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phy-handle = <&phy8>;
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};
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port@1 {
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reg = <1>;
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phy-mode = "internal";
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phy-handle = <&phy9>;
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};
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port@2 {
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reg = <2>;
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phy-mode = "internal";
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phy-handle = <&phy10>;
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};
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port@3 {
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reg = <3>;
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@8 {
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reg = <8>;
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phy-mode = "internal";
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ethernet = <&enet>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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mdio: mdio@405c0 {
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compatible = "brcm,unimac-mdio";
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reg = <0x405c0 0x8>;
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reg-names = "mdio";
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#size-cells = <0>;
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#address-cells = <1>;
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phy8: ethernet-phy@8 {
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reg = <8>;
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};
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phy9: ethernet-phy@9 {
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reg = <9>;
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};
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phy10: ethernet-phy@a {
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reg = <10>;
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};
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phy11: ethernet-phy@b {
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reg = <11>;
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};
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phy12: ethernet-phy@c {
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reg = <12>;
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};
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};
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};
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procmon: syscon@280000 {
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compatible = "simple-bus";
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reg = <0x280000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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pmb: power-controller@2800c0 {
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compatible = "brcm,bcm4908-pmb";
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reg = <0x2800c0 0x40>;
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#power-domain-cells = <1>;
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};
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0xff800000 0x3000>;
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twd: timer-mfd@400 {
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compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
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reg = <0x400 0x4c>;
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};
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gpio0: gpio-controller@500 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x500 0x28>, <0x528 0x28>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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uart0: serial@640 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x640 0x18>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "okay";
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};
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nand@1800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
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reg = <0x1800 0x600>, <0x2000 0x10>;
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reg-names = "nand", "nand-int-base";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "nand";
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status = "okay";
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nandcs: nand@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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};
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};
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misc@2600 {
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compatible = "brcm,misc", "simple-mfd";
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reg = <0x2600 0xe4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x2600 0xe4>;
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reset-controller@2644 {
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compatible = "brcm,bcm4908-misc-pcie-reset";
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reg = <0x44 0x04>;
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#reset-cells = <1>;
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};
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};
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&twd>;
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offset = <0x34>;
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mask = <1>;
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};
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};
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