Thierry Reding fed0289394 gpu: host1x: debug: Dump DMASTART and DMAEND register ...

Show the values of the DMASTART and DMAEND registers when dumping status
to help with failure analysis.

Signed-off-by: Thierry Reding <treding@nvidia.com>

2021-08-13 18:23:32 +02:00

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cdma_hw.c

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channel_hw.c

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debug_hw_1x01.c

gpu: host1x: debug: Dump DMASTART and DMAEND register

2021-08-13 18:23:32 +02:00

debug_hw_1x06.c

gpu: host1x: debug: Dump DMASTART and DMAEND register

2021-08-13 18:23:32 +02:00

debug_hw.c

gpu: host1x: debug: Dump only relevant parts of CDMA push buffer

2021-08-13 18:23:32 +02:00

host1x01_hardware.h

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host1x01.c

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host1x01.h

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host1x02_hardware.h

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host1x02.c

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host1x02.h

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host1x04_hardware.h

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host1x04.c

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host1x04.h

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host1x05_hardware.h

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host1x05.c

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host1x05.h

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host1x06_hardware.h

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host1x06.c

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host1x06.h

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host1x07_hardware.h

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host1x07.c

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host1x07.h

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hw_host1x01_channel.h

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hw_host1x01_sync.h

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hw_host1x01_uclass.h

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hw_host1x02_channel.h

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hw_host1x02_sync.h

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hw_host1x02_uclass.h

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hw_host1x04_channel.h

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hw_host1x04_sync.h

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hw_host1x04_uclass.h

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hw_host1x05_channel.h

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hw_host1x05_sync.h

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hw_host1x05_uclass.h

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hw_host1x06_channel.h

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hw_host1x06_hypervisor.h

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hw_host1x06_uclass.h

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hw_host1x06_vm.h

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hw_host1x07_channel.h

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hw_host1x07_hypervisor.h

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hw_host1x07_uclass.h

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hw_host1x07_vm.h

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intr_hw.c

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syncpt_hw.c

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