660df4411e
[ Upstream commit 3a1a274e933fca73fdc960cb1f60636cd285a265 ]
This patch adds logic to compute the MDIO period based on
the i1clk, and thereafter write the MDIO period into the YU
MDIO config register. The i1clk resource from the ACPI table
is used to provide addressing to YU bootrecord PLL registers.
The values in these registers are used to compute MDIO period.
If the i1clk resource is not present in the ACPI table, then
the current default hardcorded value of 430Mhz is used.
The i1clk clock value of 430MHz is only accurate for boards
with BF2 mid bin and main bin SoCs. The BF2 high bin SoCs
have i1clk = 500MHz, but can support a slower MDIO period.
Fixes: f92e1869d7 ("Add Mellanox BlueField Gigabit Ethernet driver")
Reviewed-by: Asmaa Mnebhi <asmaa@nvidia.com>
Signed-off-by: David Thompson <davthompson@nvidia.com>
Link: https://lore.kernel.org/r/20220826155916.12491-1-davthompson@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
193 lines
6.2 KiB
C
193 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/* Header file for Gigabit Ethernet driver for Mellanox BlueField SoC
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* - this file contains software data structures and any chip-specific
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* data structures (e.g. TX WQE format) that are memory resident.
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*
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* Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
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*/
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#ifndef __MLXBF_GIGE_H__
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#define __MLXBF_GIGE_H__
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/irqreturn.h>
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#include <linux/netdevice.h>
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#include <linux/irq.h>
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/* The silicon design supports a maximum RX ring size of
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* 32K entries. Based on current testing this maximum size
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* is not required to be supported. Instead the RX ring
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* will be capped at a realistic value of 1024 entries.
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*/
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#define MLXBF_GIGE_MIN_RXQ_SZ 32
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#define MLXBF_GIGE_MAX_RXQ_SZ 1024
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#define MLXBF_GIGE_DEFAULT_RXQ_SZ 128
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#define MLXBF_GIGE_MIN_TXQ_SZ 4
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#define MLXBF_GIGE_MAX_TXQ_SZ 256
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#define MLXBF_GIGE_DEFAULT_TXQ_SZ 128
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#define MLXBF_GIGE_DEFAULT_BUF_SZ 2048
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#define MLXBF_GIGE_DMA_PAGE_SZ 4096
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#define MLXBF_GIGE_DMA_PAGE_SHIFT 12
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/* There are four individual MAC RX filters. Currently
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* two of them are being used: one for the broadcast MAC
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* (index 0) and one for local MAC (index 1)
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*/
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#define MLXBF_GIGE_BCAST_MAC_FILTER_IDX 0
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#define MLXBF_GIGE_LOCAL_MAC_FILTER_IDX 1
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/* Define for broadcast MAC literal */
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#define BCAST_MAC_ADDR 0xFFFFFFFFFFFF
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/* There are three individual interrupts:
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* 1) Errors, "OOB" interrupt line
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* 2) Receive Packet, "OOB_LLU" interrupt line
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* 3) LLU and PLU Events, "OOB_PLU" interrupt line
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*/
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#define MLXBF_GIGE_ERROR_INTR_IDX 0
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#define MLXBF_GIGE_RECEIVE_PKT_INTR_IDX 1
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#define MLXBF_GIGE_LLU_PLU_INTR_IDX 2
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#define MLXBF_GIGE_PHY_INT_N 3
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#define MLXBF_GIGE_MDIO_DEFAULT_PHY_ADDR 0x3
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#define MLXBF_GIGE_DEFAULT_PHY_INT_GPIO 12
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struct mlxbf_gige_stats {
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u64 hw_access_errors;
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u64 tx_invalid_checksums;
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u64 tx_small_frames;
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u64 tx_index_errors;
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u64 sw_config_errors;
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u64 sw_access_errors;
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u64 rx_truncate_errors;
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u64 rx_mac_errors;
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u64 rx_din_dropped_pkts;
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u64 tx_fifo_full;
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u64 rx_filter_passed_pkts;
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u64 rx_filter_discard_pkts;
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};
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struct mlxbf_gige {
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void __iomem *base;
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void __iomem *llu_base;
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void __iomem *plu_base;
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struct device *dev;
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struct net_device *netdev;
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struct platform_device *pdev;
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void __iomem *mdio_io;
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void __iomem *clk_io;
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struct mii_bus *mdiobus;
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void __iomem *gpio_io;
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struct irq_domain *irqdomain;
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u32 phy_int_gpio_mask;
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spinlock_t lock; /* for packet processing indices */
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spinlock_t gpio_lock; /* for GPIO bus access */
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u16 rx_q_entries;
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u16 tx_q_entries;
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u64 *tx_wqe_base;
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dma_addr_t tx_wqe_base_dma;
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u64 *tx_wqe_next;
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u64 *tx_cc;
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dma_addr_t tx_cc_dma;
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dma_addr_t *rx_wqe_base;
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dma_addr_t rx_wqe_base_dma;
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u64 *rx_cqe_base;
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dma_addr_t rx_cqe_base_dma;
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u16 tx_pi;
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u16 prev_tx_ci;
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u64 error_intr_count;
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u64 rx_intr_count;
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u64 llu_plu_intr_count;
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struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ];
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struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ];
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int error_irq;
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int rx_irq;
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int llu_plu_irq;
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int phy_irq;
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int hw_phy_irq;
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bool promisc_enabled;
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u8 valid_polarity;
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struct napi_struct napi;
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struct mlxbf_gige_stats stats;
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};
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/* Rx Work Queue Element definitions */
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#define MLXBF_GIGE_RX_WQE_SZ 8
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/* Rx Completion Queue Element definitions */
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#define MLXBF_GIGE_RX_CQE_SZ 8
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#define MLXBF_GIGE_RX_CQE_PKT_LEN_MASK GENMASK(10, 0)
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#define MLXBF_GIGE_RX_CQE_VALID_MASK GENMASK(11, 11)
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#define MLXBF_GIGE_RX_CQE_PKT_STATUS_MASK GENMASK(15, 12)
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#define MLXBF_GIGE_RX_CQE_PKT_STATUS_MAC_ERR GENMASK(12, 12)
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#define MLXBF_GIGE_RX_CQE_PKT_STATUS_TRUNCATED GENMASK(13, 13)
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#define MLXBF_GIGE_RX_CQE_CHKSUM_MASK GENMASK(31, 16)
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/* Tx Work Queue Element definitions */
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#define MLXBF_GIGE_TX_WQE_SZ_QWORDS 2
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#define MLXBF_GIGE_TX_WQE_SZ 16
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#define MLXBF_GIGE_TX_WQE_PKT_LEN_MASK GENMASK(10, 0)
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#define MLXBF_GIGE_TX_WQE_UPDATE_MASK GENMASK(31, 31)
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#define MLXBF_GIGE_TX_WQE_CHKSUM_LEN_MASK GENMASK(42, 32)
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#define MLXBF_GIGE_TX_WQE_CHKSUM_START_MASK GENMASK(55, 48)
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#define MLXBF_GIGE_TX_WQE_CHKSUM_OFFSET_MASK GENMASK(63, 56)
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/* Macro to return packet length of specified TX WQE */
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#define MLXBF_GIGE_TX_WQE_PKT_LEN(tx_wqe_addr) \
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(*((tx_wqe_addr) + 1) & MLXBF_GIGE_TX_WQE_PKT_LEN_MASK)
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/* Tx Completion Count */
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#define MLXBF_GIGE_TX_CC_SZ 8
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/* List of resources in ACPI table */
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enum mlxbf_gige_res {
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MLXBF_GIGE_RES_MAC,
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MLXBF_GIGE_RES_MDIO9,
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MLXBF_GIGE_RES_GPIO0,
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MLXBF_GIGE_RES_LLU,
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MLXBF_GIGE_RES_PLU,
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MLXBF_GIGE_RES_CLK
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};
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/* Version of register data returned by mlxbf_gige_get_regs() */
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#define MLXBF_GIGE_REGS_VERSION 1
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int mlxbf_gige_mdio_probe(struct platform_device *pdev,
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struct mlxbf_gige *priv);
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void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv);
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irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id);
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void mlxbf_gige_mdio_enable_phy_int(struct mlxbf_gige *priv);
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void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv,
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unsigned int index, u64 dmac);
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void mlxbf_gige_get_mac_rx_filter(struct mlxbf_gige *priv,
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unsigned int index, u64 *dmac);
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void mlxbf_gige_enable_promisc(struct mlxbf_gige *priv);
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void mlxbf_gige_disable_promisc(struct mlxbf_gige *priv);
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int mlxbf_gige_rx_init(struct mlxbf_gige *priv);
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void mlxbf_gige_rx_deinit(struct mlxbf_gige *priv);
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int mlxbf_gige_tx_init(struct mlxbf_gige *priv);
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void mlxbf_gige_tx_deinit(struct mlxbf_gige *priv);
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bool mlxbf_gige_handle_tx_complete(struct mlxbf_gige *priv);
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netdev_tx_t mlxbf_gige_start_xmit(struct sk_buff *skb,
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struct net_device *netdev);
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struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
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unsigned int map_len,
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dma_addr_t *buf_dma,
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enum dma_data_direction dir);
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int mlxbf_gige_request_irqs(struct mlxbf_gige *priv);
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void mlxbf_gige_free_irqs(struct mlxbf_gige *priv);
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int mlxbf_gige_poll(struct napi_struct *napi, int budget);
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extern const struct ethtool_ops mlxbf_gige_ethtool_ops;
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void mlxbf_gige_update_tx_wqe_next(struct mlxbf_gige *priv);
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int mlxbf_gige_gpio_init(struct platform_device *pdev, struct mlxbf_gige *priv);
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void mlxbf_gige_gpio_free(struct mlxbf_gige *priv);
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#endif /* !defined(__MLXBF_GIGE_H__) */
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