390d1b461e
Instead of using the lantiq specific MIPS_CPU_TIMER_IRQ use the generic CP0_LEGACY_COMPARE_IRQ constant for the timer interrupt number. MIPS_CPU_TIMER_IRQ was already defined to 7 for both supported SoC families. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: jhogan@kernel.org Cc: ralf@linux-mips.org Cc: john@phrozen.org Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org
25 lines
701 B
C
25 lines
701 B
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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*/
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#ifndef _LANTIQ_XWAY_IRQ_H__
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#define _LANTIQ_XWAY_IRQ_H__
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#define INT_NUM_IRQ0 8
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#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
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#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
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#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
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#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
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#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
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#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
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#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define MAX_IM 5
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#endif
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