d0f482bb06
This provides the configuration for the currently available evaluation boards PCB134 and PCB135. The series depends on the following series currently on its way into the kernel: - Sparx5 Reset Driver Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegelund@microchip.com/ Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
481 lines
11 KiB
Plaintext
481 lines
11 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/microchip,sparx5.h>
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/ {
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compatible = "microchip,sparx5";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <1>;
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aliases {
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spi0 = &spi0;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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lcpll_clk: lcpll-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <2500000000>;
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};
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clks: clock-controller@61110000c {
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compatible = "microchip,sparx5-dpll";
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#clock-cells = <1>;
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clocks = <&lcpll_clk>;
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reg = <0x6 0x1110000c 0x24>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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sys_clk: sys-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <625000000>;
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};
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axi: axi@600000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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gic: interrupt-controller@600300000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller;
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reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
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<0x6 0x00340000 0xc0000>, /* GICR */
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<0x6 0x00200000 0x2000>, /* GICC */
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<0x6 0x00210000 0x2000>, /* GICV */
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<0x6 0x00220000 0x2000>; /* GICH */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpu_ctrl: syscon@600000000 {
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compatible = "microchip,sparx5-cpu-syscon", "syscon",
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"simple-mfd";
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reg = <0x6 0x00000000 0xd0>;
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mux: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <0>;
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/*
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* SI_OWNER and SI2_OWNER in GENERAL_CTRL
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* SPI: value 9 - (SIMC,SIBM) = 0b1001
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* SPI2: value 6 - (SIBM,SIMC) = 0b0110
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*/
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mux-reg-masks = <0x88 0xf0>;
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};
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};
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reset: reset-controller@611010008 {
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compatible = "microchip,sparx5-switch-reset";
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reg = <0x6 0x11010008 0x4>;
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reg-names = "gcb";
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#reset-cells = <1>;
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cpu-syscon = <&cpu_ctrl>;
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};
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uart0: serial@600100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x6 0x00100000 0x20>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@600102000 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x6 0x00102000 0x20>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi0: spi@600104000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "microchip,sparx5-spi";
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reg = <0x6 0x00104000 0x40>;
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num-cs = <16>;
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reg-io-width = <4>;
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reg-shift = <2>;
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clocks = <&ahb_clk>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer1: timer@600105000 {
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compatible = "snps,dw-apb-timer";
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reg = <0x6 0x00105000 0x1000>;
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clocks = <&ahb_clk>;
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clock-names = "timer";
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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sdhci0: mmc@600800000 {
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compatible = "microchip,dw-sparx5-sdhci";
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status = "disabled";
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reg = <0x6 0x00800000 0x1000>;
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pinctrl-0 = <&emmc_pins>;
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pinctrl-names = "default";
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clocks = <&clks CLK_ID_AUX1>;
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clock-names = "core";
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assigned-clocks = <&clks CLK_ID_AUX1>;
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assigned-clock-rates = <800000000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <8>;
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};
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gpio: pinctrl@6110101e0 {
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compatible = "microchip,sparx5-pinctrl";
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reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 64>;
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interrupt-controller;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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cs1_pins: cs1-pins {
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pins = "GPIO_16";
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function = "si";
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};
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cs2_pins: cs2-pins {
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pins = "GPIO_17";
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function = "si";
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};
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cs3_pins: cs3-pins {
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pins = "GPIO_18";
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function = "si";
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};
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si2_pins: si2-pins {
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pins = "GPIO_39", "GPIO_40", "GPIO_41";
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function = "si2";
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};
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sgpio0_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
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function = "sg0";
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};
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sgpio1_pins: sgpio1-pins {
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pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
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function = "sg1";
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};
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sgpio2_pins: sgpio2-pins {
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pins = "GPIO_30", "GPIO_31", "GPIO_32",
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"GPIO_33";
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function = "sg2";
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};
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uart_pins: uart-pins {
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pins = "GPIO_10", "GPIO_11";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_26", "GPIO_27";
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function = "uart2";
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};
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i2c_pins: i2c-pins {
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pins = "GPIO_14", "GPIO_15";
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function = "twi";
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};
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i2c2_pins: i2c2-pins {
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pins = "GPIO_28", "GPIO_29";
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function = "twi2";
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};
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emmc_pins: emmc-pins {
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pins = "GPIO_34", "GPIO_35", "GPIO_36",
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"GPIO_37", "GPIO_38", "GPIO_39",
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"GPIO_40", "GPIO_41", "GPIO_42",
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"GPIO_43", "GPIO_44", "GPIO_45",
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"GPIO_46", "GPIO_47";
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function = "emmc";
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};
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miim1_pins: miim1-pins {
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pins = "GPIO_56", "GPIO_57";
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function = "miim";
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};
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miim2_pins: miim2-pins {
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pins = "GPIO_58", "GPIO_59";
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function = "miim";
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};
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miim3_pins: miim3-pins {
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pins = "GPIO_52", "GPIO_53";
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function = "miim";
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};
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};
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sgpio0: gpio@61101036c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "microchip,sparx5-sgpio";
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status = "disabled";
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clocks = <&sys_clk>;
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pinctrl-0 = <&sgpio0_pins>;
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pinctrl-names = "default";
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resets = <&reset 0>;
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reset-names = "switch";
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reg = <0x6 0x1101036c 0x100>;
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sgpio_in0: gpio@0 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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sgpio_out0: gpio@1 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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};
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};
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sgpio1: gpio@611010484 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "microchip,sparx5-sgpio";
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status = "disabled";
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clocks = <&sys_clk>;
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pinctrl-0 = <&sgpio1_pins>;
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pinctrl-names = "default";
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resets = <&reset 0>;
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reset-names = "switch";
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reg = <0x6 0x11010484 0x100>;
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sgpio_in1: gpio@0 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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sgpio_out1: gpio@1 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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};
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};
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sgpio2: gpio@61101059c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "microchip,sparx5-sgpio";
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status = "disabled";
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clocks = <&sys_clk>;
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pinctrl-0 = <&sgpio2_pins>;
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pinctrl-names = "default";
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resets = <&reset 0>;
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reset-names = "switch";
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reg = <0x6 0x1101059c 0x100>;
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sgpio_in2: gpio@0 {
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reg = <0>;
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compatible = "microchip,sparx5-sgpio-bank";
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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sgpio_out2: gpio@1 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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};
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};
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i2c0: i2c@600101000 {
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compatible = "snps,designware-i2c";
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status = "disabled";
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pinctrl-0 = <&i2c_pins>;
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pinctrl-names = "default";
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reg = <0x6 0x00101000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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i2c-sda-hold-time-ns = <300>;
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clock-frequency = <100000>;
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clocks = <&ahb_clk>;
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};
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i2c1: i2c@600103000 {
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compatible = "snps,designware-i2c";
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status = "disabled";
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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reg = <0x6 0x00103000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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i2c-sda-hold-time-ns = <300>;
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clock-frequency = <100000>;
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clocks = <&ahb_clk>;
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};
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tmon0: tmon@610508110 {
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compatible = "microchip,sparx5-temp";
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reg = <0x6 0x10508110 0xc>;
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#thermal-sensor-cells = <0>;
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clocks = <&ahb_clk>;
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};
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mdio0: mdio@6110102b0 {
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compatible = "mscc,ocelot-miim";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6 0x110102b0 0x24>;
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};
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mdio1: mdio@6110102d4 {
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compatible = "mscc,ocelot-miim";
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status = "disabled";
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pinctrl-0 = <&miim1_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6 0x110102d4 0x24>;
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};
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mdio2: mdio@6110102f8 {
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compatible = "mscc,ocelot-miim";
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status = "disabled";
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pinctrl-0 = <&miim2_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6 0x110102d4 0x24>;
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};
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mdio3: mdio@61101031c {
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compatible = "mscc,ocelot-miim";
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status = "disabled";
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pinctrl-0 = <&miim3_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6 0x1101031c 0x24>;
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};
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serdes: serdes@10808000 {
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compatible = "microchip,sparx5-serdes";
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#phy-cells = <1>;
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clocks = <&sys_clk>;
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reg = <0x6 0x10808000 0x5d0000>;
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};
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switch: switch@0x600000000 {
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compatible = "microchip,sparx5-switch";
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reg = <0x6 0 0x401000>,
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<0x6 0x10004000 0x7fc000>,
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<0x6 0x11010000 0xaf0000>;
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reg-names = "cpu", "dev", "gcb";
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interrupt-names = "xtr";
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&reset 0>;
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reset-names = "switch";
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};
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};
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};
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