dd7c7ab01a
NPS customers are no longer doing active development, as evident from rand config build failures reported in recent times, so drop support for NPS platform. Tested-by: kernel test robot <lkp@intel.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
453 lines
11 KiB
C
453 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef _ASM_ARC_ATOMIC_H
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#define _ASM_ARC_ATOMIC_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#include <asm/smp.h>
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#define atomic_read(v) READ_ONCE((v)->counter)
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#ifdef CONFIG_ARC_HAS_LLSC
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#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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\
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__asm__ __volatile__( \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
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: [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
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[i] "ir" (i) \
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: "cc"); \
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} \
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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* LLOCK/SCOND thmeselves don't provide any such semantics \
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*/ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val) \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc"); \
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\
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smp_mb(); \
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\
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return val; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned int val, orig; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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* LLOCK/SCOND thmeselves don't provide any such semantics \
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*/ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: llock %[orig], [%[ctr]] \n" \
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" " #asm_op " %[val], %[orig], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val), \
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[orig] "=&r" (orig) \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc"); \
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\
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smp_mb(); \
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\
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return orig; \
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#ifndef CONFIG_SMP
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/* violating atomic_xxx API locking protocol in UP for optimization sake */
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#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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#else
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static inline void atomic_set(atomic_t *v, int i)
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{
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/*
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* Independent of hardware support, all of the atomic_xxx() APIs need
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* to follow the same locking rules to make sure that a "hardware"
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* atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
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* sequence
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*
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* Thus atomic_set() despite being 1 insn (and seemingly atomic)
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* requires the locking.
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*/
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unsigned long flags;
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atomic_ops_lock(flags);
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WRITE_ONCE(v->counter, i);
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atomic_ops_unlock(flags);
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}
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#define atomic_set_release(v, i) atomic_set((v), (i))
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#endif
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/*
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* Non hardware assisted Atomic-R-M-W
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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*/
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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\
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atomic_ops_lock(flags); \
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v->counter c_op i; \
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atomic_ops_unlock(flags); \
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}
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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unsigned long temp; \
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\
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/* \
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* spin lock/unlock provides the needed smp_mb() before/after \
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*/ \
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atomic_ops_lock(flags); \
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temp = v->counter; \
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temp c_op i; \
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v->counter = temp; \
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atomic_ops_unlock(flags); \
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\
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return temp; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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unsigned long orig; \
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\
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/* \
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* spin lock/unlock provides the needed smp_mb() before/after \
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*/ \
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atomic_ops_lock(flags); \
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orig = v->counter; \
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v->counter c_op i; \
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atomic_ops_unlock(flags); \
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\
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return orig; \
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}
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#endif /* !CONFIG_ARC_HAS_LLSC */
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, add)
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ATOMIC_OPS(sub, -=, sub)
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#define atomic_andnot atomic_andnot
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#define atomic_fetch_andnot atomic_fetch_andnot
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(andnot, &= ~, bic)
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ATOMIC_OPS(or, |=, or)
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ATOMIC_OPS(xor, ^=, xor)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#ifdef CONFIG_GENERIC_ATOMIC64
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#include <asm-generic/atomic64.h>
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#else /* Kconfig ensures this is only enabled with needed h/w assist */
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/*
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* ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
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* - The address HAS to be 64-bit aligned
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* - There are 2 semantics involved here:
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* = exclusive implies no interim update between load/store to same addr
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* = both words are observed/updated together: this is guaranteed even
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* for regular 64-bit load (LDD) / store (STD). Thus atomic64_set()
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* is NOT required to use LLOCKD+SCONDD, STD suffices
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*/
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typedef struct {
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s64 __aligned(8) counter;
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} atomic64_t;
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#define ATOMIC64_INIT(a) { (a) }
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static inline s64 atomic64_read(const atomic64_t *v)
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{
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s64 val;
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__asm__ __volatile__(
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" ldd %0, [%1] \n"
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: "=r"(val)
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: "r"(&v->counter));
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return val;
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}
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static inline void atomic64_set(atomic64_t *v, s64 a)
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{
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/*
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* This could have been a simple assignment in "C" but would need
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* explicit volatile. Otherwise gcc optimizers could elide the store
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* which borked atomic64 self-test
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* In the inline asm version, memory clobber needed for exact same
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* reason, to tell gcc about the store.
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*
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* This however is not needed for sibling atomic64_add() etc since both
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* load/store are explicitly done in inline asm. As long as API is used
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* for each access, gcc has no way to optimize away any load/store
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*/
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__asm__ __volatile__(
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" std %0, [%1] \n"
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:
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: "r"(a), "r"(&v->counter)
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: "memory");
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}
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#define ATOMIC64_OP(op, op1, op2) \
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static inline void atomic64_##op(s64 a, atomic64_t *v) \
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{ \
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s64 val; \
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\
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__asm__ __volatile__( \
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"1: \n" \
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" llockd %0, [%1] \n" \
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" " #op1 " %L0, %L0, %L2 \n" \
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" " #op2 " %H0, %H0, %H2 \n" \
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" scondd %0, [%1] \n" \
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" bnz 1b \n" \
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: "=&r"(val) \
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: "r"(&v->counter), "ir"(a) \
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: "cc"); \
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} \
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#define ATOMIC64_OP_RETURN(op, op1, op2) \
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static inline s64 atomic64_##op##_return(s64 a, atomic64_t *v) \
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{ \
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s64 val; \
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\
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: \n" \
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" llockd %0, [%1] \n" \
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" " #op1 " %L0, %L0, %L2 \n" \
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" " #op2 " %H0, %H0, %H2 \n" \
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" scondd %0, [%1] \n" \
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" bnz 1b \n" \
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: [val] "=&r"(val) \
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: "r"(&v->counter), "ir"(a) \
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: "cc"); /* memory clobber comes from smp_mb() */ \
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\
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smp_mb(); \
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\
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return val; \
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}
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#define ATOMIC64_FETCH_OP(op, op1, op2) \
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static inline s64 atomic64_fetch_##op(s64 a, atomic64_t *v) \
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{ \
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s64 val, orig; \
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\
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: \n" \
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" llockd %0, [%2] \n" \
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" " #op1 " %L1, %L0, %L3 \n" \
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" " #op2 " %H1, %H0, %H3 \n" \
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" scondd %1, [%2] \n" \
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" bnz 1b \n" \
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: "=&r"(orig), "=&r"(val) \
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: "r"(&v->counter), "ir"(a) \
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: "cc"); /* memory clobber comes from smp_mb() */ \
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\
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smp_mb(); \
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\
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return orig; \
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}
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#define ATOMIC64_OPS(op, op1, op2) \
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ATOMIC64_OP(op, op1, op2) \
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ATOMIC64_OP_RETURN(op, op1, op2) \
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ATOMIC64_FETCH_OP(op, op1, op2)
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#define atomic64_andnot atomic64_andnot
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#define atomic64_fetch_andnot atomic64_fetch_andnot
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ATOMIC64_OPS(add, add.f, adc)
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ATOMIC64_OPS(sub, sub.f, sbc)
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ATOMIC64_OPS(and, and, and)
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ATOMIC64_OPS(andnot, bic, bic)
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ATOMIC64_OPS(or, or, or)
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ATOMIC64_OPS(xor, xor, xor)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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static inline s64
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atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new)
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{
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s64 prev;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%1] \n"
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" brne %L0, %L2, 2f \n"
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" brne %H0, %H2, 2f \n"
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" scondd %3, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(prev)
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: "r"(ptr), "ir"(expected), "r"(new)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return prev;
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}
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static inline s64 atomic64_xchg(atomic64_t *ptr, s64 new)
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{
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s64 prev;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%1] \n"
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" scondd %2, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(prev)
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: "r"(ptr), "r"(new)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return prev;
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}
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/**
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* atomic64_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic64_t
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*
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* The function returns the old value of *v minus 1, even if
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* the atomic variable, v, was not decremented.
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*/
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static inline s64 atomic64_dec_if_positive(atomic64_t *v)
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{
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s64 val;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%1] \n"
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" sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n"
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" sub.c %H0, %H0, 1 # if C set, w1 - 1\n"
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" brlt %H0, 0, 2f \n"
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" scondd %0, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(val)
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: "r"(&v->counter)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return val;
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}
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#define atomic64_dec_if_positive atomic64_dec_if_positive
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/**
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* atomic64_fetch_add_unless - add unless the number is a given value
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* @v: pointer of type atomic64_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, if it was not @u.
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* Returns the old value of @v
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*/
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static inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
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{
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s64 old, temp;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%2] \n"
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" brne %L0, %L4, 2f # continue to add since v != u \n"
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" breq.d %H0, %H4, 3f # return since v == u \n"
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"2: \n"
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" add.f %L1, %L0, %L3 \n"
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" adc %H1, %H0, %H3 \n"
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" scondd %1, [%2] \n"
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" bnz 1b \n"
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"3: \n"
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: "=&r"(old), "=&r" (temp)
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: "r"(&v->counter), "r"(a), "r"(u)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return old;
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}
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#define atomic64_fetch_add_unless atomic64_fetch_add_unless
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#endif /* !CONFIG_GENERIC_ATOMIC64 */
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#endif /* !__ASSEMBLY__ */
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#endif
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