Merge 5.15.80 into android14-5.15
Changes in 5.15.80 mm: hwpoison: refactor refcount check handling mm: hwpoison: handle non-anonymous THP correctly mm: shmem: don't truncate page if memory failure happens ASoC: wm5102: Revert "ASoC: wm5102: Fix PM disable depth imbalance in wm5102_probe" ASoC: wm5110: Revert "ASoC: wm5110: Fix PM disable depth imbalance in wm5110_probe" ASoC: wm8997: Revert "ASoC: wm8997: Fix PM disable depth imbalance in wm8997_probe" ASoC: mt6660: Keep the pm_runtime enables before component stuff in mt6660_i2c_probe ASoC: rt1019: Fix the TDM settings ASoC: wm8962: Add an event handler for TEMP_HP and TEMP_SPK spi: intel: Fix the offset to get the 64K erase opcode ASoC: codecs: jz4725b: add missed Line In power control bit ASoC: codecs: jz4725b: fix reported volume for Master ctl ASoC: codecs: jz4725b: use right control for Capture Volume ASoC: codecs: jz4725b: fix capture selector naming ASoC: Intel: sof_sdw: add quirk variant for LAPBC710 NUC15 selftests/futex: fix build for clang selftests/intel_pstate: fix build for ARCH=x86_64 ASoC: rt1308-sdw: add the default value of some registers drm/amd/display: Remove wrong pipe control lock ACPI: scan: Add LATT2021 to acpi_ignore_dep_ids[] RDMA/efa: Add EFA 0xefa2 PCI ID btrfs: raid56: properly handle the error when unable to find the missing stripe NFSv4: Retry LOCK on OLD_STATEID during delegation return ACPI: x86: Add another system to quirk list for forcing StorageD3Enable firmware: arm_scmi: Cleanup the core driver removal callback i2c: tegra: Allocate DMA memory for DMA engine i2c: i801: add lis3lv02d's I2C address for Vostro 5568 drm/imx: imx-tve: Fix return type of imx_tve_connector_mode_valid btrfs: remove pointless and double ulist frees in error paths of qgroup tests Bluetooth: L2CAP: Fix l2cap_global_chan_by_psm x86/cpu: Add several Intel server CPU model numbers ASoC: codecs: jz4725b: Fix spelling mistake "Sourc" -> "Source", "Routee" -> "Route" mtd: spi-nor: intel-spi: Disable write protection only if asked spi: intel: Use correct mask for flash and protected regions KVM: x86/pmu: Do not speculatively query Intel GP PMCs that don't exist yet hugetlbfs: don't delete error page from pagecache arm64: dts: qcom: sa8155p-adp: Specify which LDO modes are allowed arm64: dts: qcom: sm8150-xperia-kumano: Specify which LDO modes are allowed arm64: dts: qcom: sm8250-xperia-edo: Specify which LDO modes are allowed arm64: dts: qcom: sm8350-hdk: Specify which LDO modes are allowed spi: stm32: Print summary 'callbacks suppressed' message ARM: dts: at91: sama7g5: fix signal name of pin PB2 ASoC: core: Fix use-after-free in snd_soc_exit() ASoC: tas2770: Fix set_tdm_slot in case of single slot ASoC: tas2764: Fix set_tdm_slot in case of single slot ARM: at91: pm: avoid soft resetting AC DLL serial: 8250: omap: Fix missing PM runtime calls for omap8250_set_mctrl() serial: 8250_omap: remove wait loop from Errata i202 workaround serial: 8250: omap: Fix unpaired pm_runtime_put_sync() in omap8250_remove() serial: 8250: omap: Flush PM QOS work on remove serial: imx: Add missing .thaw_noirq hook tty: n_gsm: fix sleep-in-atomic-context bug in gsm_control_send bpf, test_run: Fix alignment problem in bpf_prog_test_run_skb() ASoC: soc-utils: Remove __exit for snd_soc_util_exit() pinctrl: rockchip: list all pins in a possible mux route for PX30 scsi: scsi_transport_sas: Fix error handling in sas_phy_add() block: sed-opal: kmalloc the cmd/resp buffers bpf: Fix memory leaks in __check_func_call arm64: Fix bit-shifting UB in the MIDR_CPU_MODEL() macro siox: fix possible memory leak in siox_device_add() parport_pc: Avoid FIFO port location truncation pinctrl: devicetree: fix null pointer dereferencing in pinctrl_dt_to_map drm/vc4: kms: Fix IS_ERR() vs NULL check for vc4_kms drm/panel: simple: set bpc field for logic technologies displays drm/drv: Fix potential memory leak in drm_dev_init() drm: Fix potential null-ptr-deref in drm_vblank_destroy_worker() ARM: dts: imx7: Fix NAND controller size-cells arm64: dts: imx8mm: Fix NAND controller size-cells arm64: dts: imx8mn: Fix NAND controller size-cells ata: libata-transport: fix double ata_host_put() in ata_tport_add() ata: libata-transport: fix error handling in ata_tport_add() ata: libata-transport: fix error handling in ata_tlink_add() ata: libata-transport: fix error handling in ata_tdev_add() nfp: change eeprom length to max length enumerators MIPS: fix duplicate definitions for exported symbols MIPS: Loongson64: Add WARN_ON on kexec related kmalloc failed bpf: Initialize same number of free nodes for each pcpu_freelist net: bgmac: Drop free_netdev() from bgmac_enet_remove() mISDN: fix possible memory leak in mISDN_dsp_element_register() net: hinic: Fix error handling in hinic_module_init() net: stmmac: ensure tx function is not running in stmmac_xdp_release() soc: imx8m: Enable OCOTP clock before reading the register net: liquidio: release resources when liquidio driver open failed mISDN: fix misuse of put_device() in mISDN_register_device() net: macvlan: Use built-in RCU list checking net: caif: fix double disconnect client in chnl_net_open() bnxt_en: Remove debugfs when pci_register_driver failed net: mhi: Fix memory leak in mhi_net_dellink() net: dsa: make dsa_master_ioctl() see through port_hwtstamp_get() shims xen/pcpu: fix possible memory leak in register_pcpu() net: ionic: Fix error handling in ionic_init_module() net: ena: Fix error handling in ena_init() net: hns3: fix setting incorrect phy link ksettings for firmware in resetting process bridge: switchdev: Fix memory leaks when changing VLAN protocol drbd: use after free in drbd_create_device() platform/x86/intel: pmc: Don't unconditionally attach Intel PMC when virtualized platform/surface: aggregator: Do not check for repeated unsequenced packets cifs: add check for returning value of SMB2_close_init net: ag71xx: call phylink_disconnect_phy if ag71xx_hw_enable() fail in ag71xx_open() net/x25: Fix skb leak in x25_lapb_receive_frame() cifs: Fix wrong return value checking when GETFLAGS net: microchip: sparx5: Fix potential null-ptr-deref in sparx_stats_init() and sparx5_start() net: thunderbolt: Fix error handling in tbnet_init() cifs: add check for returning value of SMB2_set_info_init ftrace: Fix the possible incorrect kernel message ftrace: Optimize the allocation for mcount entries ftrace: Fix null pointer dereference in ftrace_add_mod() ring_buffer: Do not deactivate non-existant pages tracing: Fix memory leak in tracing_read_pipe() tracing/ring-buffer: Have polling block on watermark tracing: Fix memory leak in test_gen_synth_cmd() and test_empty_synth_event() tracing: Fix wild-memory-access in register_synth_event() tracing: Fix race where eprobes can be called before the event tracing: kprobe: Fix potential null-ptr-deref on trace_event_file in kprobe_event_gen_test_exit() tracing: kprobe: Fix potential null-ptr-deref on trace_array in kprobe_event_gen_test_exit() drm/amd/display: Add HUBP surface flip interrupt handler ALSA: usb-audio: Drop snd_BUG_ON() from snd_usbmidi_output_open() ALSA: hda/realtek: fix speakers for Samsung Galaxy Book Pro ALSA: hda/realtek: Fix the speaker output on Samsung Galaxy Book Pro 360 Revert "usb: dwc3: disable USB core PHY management" slimbus: qcom-ngd: Fix build error when CONFIG_SLIM_QCOM_NGD_CTRL=y && CONFIG_QCOM_RPROC_COMMON=m slimbus: stream: correct presence rate frequencies speakup: fix a segfault caused by switching consoles USB: bcma: Make GPIO explicitly optional USB: serial: option: add Sierra Wireless EM9191 USB: serial: option: remove old LARA-R6 PID USB: serial: option: add u-blox LARA-R6 00B modem USB: serial: option: add u-blox LARA-L6 modem USB: serial: option: add Fibocom FM160 0x0111 composition usb: add NO_LPM quirk for Realforce 87U Keyboard usb: chipidea: fix deadlock in ci_otg_del_timer usb: cdns3: host: fix endless superspeed hub port reset usb: typec: mux: Enter safe mode only when pins need to be reconfigured iio: adc: at91_adc: fix possible memory leak in at91_adc_allocate_trigger() iio: trigger: sysfs: fix possible memory leak in iio_sysfs_trig_init() iio: adc: mp2629: fix wrong comparison of channel iio: adc: mp2629: fix potential array out of bound access iio: pressure: ms5611: changed hardcoded SPI speed to value limited dm ioctl: fix misbehavior if list_versions races with module loading serial: 8250: Fall back to non-DMA Rx if IIR_RDI occurs serial: 8250: Flush DMA Rx on RLSI serial: 8250_lpss: Configure DMA also w/o DMA filter Input: iforce - invert valid length check when fetching device IDs maccess: Fix writing offset in case of fault in strncpy_from_kernel_nofault() net: phy: marvell: add sleep time after enabling the loopback bit scsi: zfcp: Fix double free of FSF request when qdio send fails iommu/vt-d: Preset Access bit for IOVA in FL non-leaf paging entries iommu/vt-d: Set SRE bit only when hardware has SRS cap firmware: coreboot: Register bus in module init mmc: core: properly select voltage range without power cycle mmc: sdhci-pci-o2micro: fix card detect fail issue caused by CD# debounce timeout mmc: sdhci-pci: Fix possible memory leak caused by missing pci_dev_put() docs: update mediator contact information in CoC doc misc/vmw_vmci: fix an infoleak in vmci_host_do_receive_datagram() perf/x86/intel/pt: Fix sampling using single range output nvme: restrict management ioctls to admin nvme: ensure subsystem reset is single threaded serial: 8250_lpss: Use 16B DMA burst with Elkhart Lake perf: Improve missing SIGTRAP checking ring-buffer: Include dropped pages in counting dirty patches tracing: Fix warning on variable 'struct trace_array' net: use struct_group to copy ip/ipv6 header addresses scsi: target: tcm_loop: Fix possible name leak in tcm_loop_setup_hba_bus() scsi: scsi_debug: Fix possible UAF in sdebug_add_host_helper() kprobes: Skip clearing aggrprobe's post_handler in kprobe-on-ftrace case Input: i8042 - fix leaking of platform device on module removal macvlan: enforce a consistent minimal mtu tcp: cdg: allow tcp_cdg_release() to be called multiple times kcm: avoid potential race in kcm_tx_work kcm: close race conditions on sk_receive_queue 9p: trans_fd/p9_conn_cancel: drop client lock earlier gfs2: Check sb_bsize_shift after reading superblock gfs2: Switch from strlcpy to strscpy 9p/trans_fd: always use O_NONBLOCK read/write wifi: wext: use flex array destination for memcpy() mm: fs: initialize fsdata passed to write_begin/write_end interface net/9p: use a dedicated spinlock for trans_fd ntfs: fix use-after-free in ntfs_attr_find() ntfs: fix out-of-bounds read in ntfs_attr_find() ntfs: check overflow when iterating ATTR_RECORDs Linux 5.15.80 Change-Id: Idc9aa4c30c528dd194bc813201cbb2c5df8c1d62 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
@@ -51,7 +51,7 @@ the Technical Advisory Board (TAB) or other maintainers if you're
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uncertain how to handle situations that come up. It will not be
|
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considered a violation report unless you want it to be. If you are
|
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uncertain about approaching the TAB or any other maintainers, please
|
||||
reach out to our conflict mediator, Joanna Lee <joanna.lee@gesmer.com>.
|
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reach out to our conflict mediator, Joanna Lee <jlee@linuxfoundation.org>.
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In the end, "be kind to each other" is really what the end goal is for
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everybody. We know everyone is human and we all fail at times, but the
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2
Makefile
2
Makefile
@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 15
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SUBLEVEL = 79
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SUBLEVEL = 80
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EXTRAVERSION =
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NAME = Trick or Treat
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@@ -1252,10 +1252,10 @@
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clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
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};
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gpmi: nand-controller@33002000{
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gpmi: nand-controller@33002000 {
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compatible = "fsl,imx7d-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <0>;
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reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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@@ -261,7 +261,7 @@
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#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1)
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#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1)
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#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1)
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#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3)
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#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3)
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#define PIN_PB3 35
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#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0)
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#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1)
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@@ -169,10 +169,15 @@ sr_ena_2:
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cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
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bne sr_ena_2
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/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
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/* Disable DX DLLs for non-backup modes. */
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cmp r7, #AT91_PM_BACKUP
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beq sr_ena_3
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/* Do not soft reset the AC DLL. */
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ldr tmp1, [r3, DDR3PHY_ACDLLCR]
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bic tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
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str tmp1, [r3, DDR3PHY_ACDLLCR]
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/* Disable DX DLLs. */
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ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
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orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
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@@ -1014,10 +1014,10 @@
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clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
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};
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gpmi: nand-controller@33002000{
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gpmi: nand-controller@33002000 {
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compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <0>;
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reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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@@ -998,7 +998,7 @@
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gpmi: nand-controller@33002000 {
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compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <0>;
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reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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@@ -43,7 +43,6 @@
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regulator-always-on;
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regulator-boot-on;
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regulator-allow-set-load;
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vin-supply = <&vreg_3p3>;
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};
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@@ -114,6 +113,9 @@
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regulator-max-microvolt = <880000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l7a_1p8: ldo7 {
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@@ -129,6 +131,9 @@
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regulator-max-microvolt = <2960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l11a_0p8: ldo11 {
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@@ -235,6 +240,9 @@
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l7c_1p8: ldo7 {
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@@ -250,6 +258,9 @@
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l10c_3p3: ldo10 {
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@@ -348,6 +348,9 @@
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regulator-max-microvolt = <2960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l7c_3p0: ldo7 {
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@@ -367,6 +370,9 @@
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regulator-max-microvolt = <2960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l10c_3p3: ldo10 {
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@@ -317,6 +317,9 @@
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regulator-max-microvolt = <2960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l7c_2p85: ldo7 {
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@@ -339,6 +342,9 @@
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regulator-max-microvolt = <2960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l10c_3p3: ldo10 {
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@@ -108,6 +108,9 @@
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regulator-max-microvolt = <888000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l6b_1p2: ldo6 {
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@@ -116,6 +119,9 @@
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regulator-max-microvolt = <1208000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l7b_2p96: ldo7 {
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@@ -124,6 +130,9 @@
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regulator-max-microvolt = <2504000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l9b_1p2: ldo9 {
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@@ -132,6 +141,9 @@
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-allow-set-load;
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regulator-allowed-modes =
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<RPMH_REGULATOR_MODE_LPM
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RPMH_REGULATOR_MODE_HPM>;
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};
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};
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@@ -41,7 +41,7 @@
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(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_CPU_MODEL(imp, partnum) \
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(((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
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((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
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(0xf << MIDR_ARCHITECTURE_SHIFT) | \
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((partnum) << MIDR_PARTNUM_SHIFT))
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@@ -145,8 +145,7 @@ LEAF(kexec_smp_wait)
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* kexec_args[0..3] are used to prepare register values.
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*/
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kexec_args:
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EXPORT(kexec_args)
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EXPORT(kexec_args)
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arg0: PTR_WD 0x0
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arg1: PTR_WD 0x0
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arg2: PTR_WD 0x0
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@@ -159,8 +158,7 @@ arg3: PTR_WD 0x0
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* their registers a0-a3. secondary_kexec_args[0..3] are used
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* to prepare register values.
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*/
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secondary_kexec_args:
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EXPORT(secondary_kexec_args)
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EXPORT(secondary_kexec_args)
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s_arg0: PTR_WD 0x0
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s_arg1: PTR_WD 0x0
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s_arg2: PTR_WD 0x0
|
||||
@@ -171,19 +169,16 @@ kexec_flag:
|
||||
|
||||
#endif
|
||||
|
||||
kexec_start_address:
|
||||
EXPORT(kexec_start_address)
|
||||
EXPORT(kexec_start_address)
|
||||
PTR_WD 0x0
|
||||
.size kexec_start_address, PTRSIZE
|
||||
|
||||
kexec_indirection_page:
|
||||
EXPORT(kexec_indirection_page)
|
||||
EXPORT(kexec_indirection_page)
|
||||
PTR_WD 0
|
||||
.size kexec_indirection_page, PTRSIZE
|
||||
|
||||
relocate_new_kernel_end:
|
||||
|
||||
relocate_new_kernel_size:
|
||||
EXPORT(relocate_new_kernel_size)
|
||||
EXPORT(relocate_new_kernel_size)
|
||||
PTR_WD relocate_new_kernel_end - relocate_new_kernel
|
||||
.size relocate_new_kernel_size, PTRSIZE
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/bug.h>
|
||||
|
||||
#include <loongson.h>
|
||||
#include <boot_param.h>
|
||||
@@ -159,8 +160,17 @@ static int __init mips_reboot_setup(void)
|
||||
|
||||
#ifdef CONFIG_KEXEC
|
||||
kexec_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
|
||||
if (WARN_ON(!kexec_argv))
|
||||
return -ENOMEM;
|
||||
|
||||
kdump_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
|
||||
if (WARN_ON(!kdump_argv))
|
||||
return -ENOMEM;
|
||||
|
||||
kexec_envp = kmalloc(KEXEC_ENVP_SIZE, GFP_KERNEL);
|
||||
if (WARN_ON(!kexec_envp))
|
||||
return -ENOMEM;
|
||||
|
||||
fw_arg1 = KEXEC_ARGV_ADDR;
|
||||
memcpy(kexec_envp, (void *)fw_arg2, KEXEC_ENVP_SIZE);
|
||||
|
||||
|
||||
@@ -1247,6 +1247,15 @@ static int pt_buffer_try_single(struct pt_buffer *buf, int nr_pages)
|
||||
if (1 << order != nr_pages)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* Some processors cannot always support single range for more than
|
||||
* 4KB - refer errata TGL052, ADL037 and RPL017. Future processors might
|
||||
* also be affected, so for now rather than trying to keep track of
|
||||
* which ones, just disable it for all.
|
||||
*/
|
||||
if (nr_pages > 1)
|
||||
goto out;
|
||||
|
||||
buf->single = true;
|
||||
buf->nr_pages = nr_pages;
|
||||
ret = 0;
|
||||
|
||||
@@ -105,10 +105,15 @@
|
||||
|
||||
#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
|
||||
|
||||
#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF
|
||||
|
||||
#define INTEL_FAM6_GRANITERAPIDS_X 0xAD
|
||||
#define INTEL_FAM6_GRANITERAPIDS_D 0xAE
|
||||
|
||||
#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
|
||||
#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
|
||||
|
||||
/* "Small Core" Processors (Atom) */
|
||||
/* "Small Core" Processors (Atom/E-Core) */
|
||||
|
||||
#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
|
||||
#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
|
||||
@@ -135,6 +140,10 @@
|
||||
#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
|
||||
#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
|
||||
|
||||
#define INTEL_FAM6_SIERRAFOREST_X 0xAF
|
||||
|
||||
#define INTEL_FAM6_GRANDRIDGE 0xB6
|
||||
|
||||
/* Xeon Phi */
|
||||
|
||||
#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
|
||||
|
||||
@@ -1347,20 +1347,10 @@ static const u32 msrs_to_save_all[] = {
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
|
||||
|
||||
MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
|
||||
MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
|
||||
@@ -6449,12 +6439,12 @@ static void kvm_init_msr_list(void)
|
||||
intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
|
||||
continue;
|
||||
break;
|
||||
case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
|
||||
case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 7:
|
||||
if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
|
||||
min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
|
||||
continue;
|
||||
break;
|
||||
case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
|
||||
case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7:
|
||||
if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
|
||||
min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
|
||||
continue;
|
||||
|
||||
@@ -88,8 +88,8 @@ struct opal_dev {
|
||||
u64 lowest_lba;
|
||||
|
||||
size_t pos;
|
||||
u8 cmd[IO_BUFFER_LENGTH];
|
||||
u8 resp[IO_BUFFER_LENGTH];
|
||||
u8 *cmd;
|
||||
u8 *resp;
|
||||
|
||||
struct parsed_resp parsed;
|
||||
size_t prev_d_len;
|
||||
@@ -2134,6 +2134,8 @@ void free_opal_dev(struct opal_dev *dev)
|
||||
return;
|
||||
|
||||
clean_opal_dev(dev);
|
||||
kfree(dev->resp);
|
||||
kfree(dev->cmd);
|
||||
kfree(dev);
|
||||
}
|
||||
EXPORT_SYMBOL(free_opal_dev);
|
||||
@@ -2146,17 +2148,39 @@ struct opal_dev *init_opal_dev(void *data, sec_send_recv *send_recv)
|
||||
if (!dev)
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
* Presumably DMA-able buffers must be cache-aligned. Kmalloc makes
|
||||
* sure the allocated buffer is DMA-safe in that regard.
|
||||
*/
|
||||
dev->cmd = kmalloc(IO_BUFFER_LENGTH, GFP_KERNEL);
|
||||
if (!dev->cmd)
|
||||
goto err_free_dev;
|
||||
|
||||
dev->resp = kmalloc(IO_BUFFER_LENGTH, GFP_KERNEL);
|
||||
if (!dev->resp)
|
||||
goto err_free_cmd;
|
||||
|
||||
INIT_LIST_HEAD(&dev->unlk_lst);
|
||||
mutex_init(&dev->dev_lock);
|
||||
dev->data = data;
|
||||
dev->send_recv = send_recv;
|
||||
if (check_opal_support(dev) != 0) {
|
||||
pr_debug("Opal is not supported on this device\n");
|
||||
kfree(dev);
|
||||
return NULL;
|
||||
goto err_free_resp;
|
||||
}
|
||||
|
||||
return dev;
|
||||
|
||||
err_free_resp:
|
||||
kfree(dev->resp);
|
||||
|
||||
err_free_cmd:
|
||||
kfree(dev->cmd);
|
||||
|
||||
err_free_dev:
|
||||
kfree(dev);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(init_opal_dev);
|
||||
|
||||
|
||||
@@ -1778,7 +1778,7 @@ static void speakup_con_update(struct vc_data *vc)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (!speakup_console[vc->vc_num] || spk_parked)
|
||||
if (!speakup_console[vc->vc_num] || spk_parked || !synth)
|
||||
return;
|
||||
if (!spin_trylock_irqsave(&speakup_info.spinlock, flags))
|
||||
/* Speakup output, discard */
|
||||
|
||||
@@ -793,6 +793,7 @@ static bool acpi_info_matches_ids(struct acpi_device_info *info,
|
||||
static const char * const acpi_ignore_dep_ids[] = {
|
||||
"PNP0D80", /* Windows-compatible System Power Management Controller */
|
||||
"INT33BD", /* Intel Baytrail Mailbox Device */
|
||||
"LATT2021", /* Lattice FW Update Client Driver */
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
@@ -210,6 +210,12 @@ static const struct dmi_system_id force_storage_d3_dmi[] = {
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14 7425 2-in-1"),
|
||||
}
|
||||
},
|
||||
{
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 16 5625"),
|
||||
}
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@@ -301,7 +301,9 @@ int ata_tport_add(struct device *parent,
|
||||
pm_runtime_enable(dev);
|
||||
pm_runtime_forbid(dev);
|
||||
|
||||
transport_add_device(dev);
|
||||
error = transport_add_device(dev);
|
||||
if (error)
|
||||
goto tport_transport_add_err;
|
||||
transport_configure_device(dev);
|
||||
|
||||
error = ata_tlink_add(&ap->link);
|
||||
@@ -312,12 +314,12 @@ int ata_tport_add(struct device *parent,
|
||||
|
||||
tport_link_err:
|
||||
transport_remove_device(dev);
|
||||
tport_transport_add_err:
|
||||
device_del(dev);
|
||||
|
||||
tport_err:
|
||||
transport_destroy_device(dev);
|
||||
put_device(dev);
|
||||
ata_host_put(ap->host);
|
||||
return error;
|
||||
}
|
||||
|
||||
@@ -426,7 +428,9 @@ int ata_tlink_add(struct ata_link *link)
|
||||
goto tlink_err;
|
||||
}
|
||||
|
||||
transport_add_device(dev);
|
||||
error = transport_add_device(dev);
|
||||
if (error)
|
||||
goto tlink_transport_err;
|
||||
transport_configure_device(dev);
|
||||
|
||||
ata_for_each_dev(ata_dev, link, ALL) {
|
||||
@@ -441,6 +445,7 @@ int ata_tlink_add(struct ata_link *link)
|
||||
ata_tdev_delete(ata_dev);
|
||||
}
|
||||
transport_remove_device(dev);
|
||||
tlink_transport_err:
|
||||
device_del(dev);
|
||||
tlink_err:
|
||||
transport_destroy_device(dev);
|
||||
@@ -678,7 +683,13 @@ static int ata_tdev_add(struct ata_device *ata_dev)
|
||||
return error;
|
||||
}
|
||||
|
||||
transport_add_device(dev);
|
||||
error = transport_add_device(dev);
|
||||
if (error) {
|
||||
device_del(dev);
|
||||
ata_tdev_free(ata_dev);
|
||||
return error;
|
||||
}
|
||||
|
||||
transport_configure_device(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -2699,7 +2699,7 @@ static int init_submitter(struct drbd_device *device)
|
||||
enum drbd_ret_code drbd_create_device(struct drbd_config_context *adm_ctx, unsigned int minor)
|
||||
{
|
||||
struct drbd_resource *resource = adm_ctx->resource;
|
||||
struct drbd_connection *connection;
|
||||
struct drbd_connection *connection, *n;
|
||||
struct drbd_device *device;
|
||||
struct drbd_peer_device *peer_device, *tmp_peer_device;
|
||||
struct gendisk *disk;
|
||||
@@ -2815,7 +2815,7 @@ enum drbd_ret_code drbd_create_device(struct drbd_config_context *adm_ctx, unsig
|
||||
return NO_ERROR;
|
||||
|
||||
out_idr_remove_from_resource:
|
||||
for_each_connection(connection, resource) {
|
||||
for_each_connection_safe(connection, n, resource) {
|
||||
peer_device = idr_remove(&connection->peer_devices, vnr);
|
||||
if (peer_device)
|
||||
kref_put(&connection->kref, drbd_destroy_connection);
|
||||
|
||||
@@ -216,9 +216,20 @@ void scmi_device_destroy(struct scmi_device *scmi_dev)
|
||||
device_unregister(&scmi_dev->dev);
|
||||
}
|
||||
|
||||
void scmi_device_link_add(struct device *consumer, struct device *supplier)
|
||||
{
|
||||
struct device_link *link;
|
||||
|
||||
link = device_link_add(consumer, supplier, DL_FLAG_AUTOREMOVE_CONSUMER);
|
||||
|
||||
WARN_ON(!link);
|
||||
}
|
||||
|
||||
void scmi_set_handle(struct scmi_device *scmi_dev)
|
||||
{
|
||||
scmi_dev->handle = scmi_handle_get(&scmi_dev->dev);
|
||||
if (scmi_dev->handle)
|
||||
scmi_device_link_add(&scmi_dev->dev, scmi_dev->handle->dev);
|
||||
}
|
||||
|
||||
int scmi_protocol_register(const struct scmi_protocol *proto)
|
||||
|
||||
@@ -272,6 +272,7 @@ struct scmi_xfer_ops {
|
||||
struct scmi_revision_info *
|
||||
scmi_revision_area_get(const struct scmi_protocol_handle *ph);
|
||||
int scmi_handle_put(const struct scmi_handle *handle);
|
||||
void scmi_device_link_add(struct device *consumer, struct device *supplier);
|
||||
struct scmi_handle *scmi_handle_get(struct device *dev);
|
||||
void scmi_set_handle(struct scmi_device *scmi_dev);
|
||||
void scmi_setup_protocol_implemented(const struct scmi_protocol_handle *ph,
|
||||
|
||||
@@ -1731,10 +1731,16 @@ int scmi_protocol_device_request(const struct scmi_device_id *id_table)
|
||||
sdev = scmi_get_protocol_device(child, info,
|
||||
id_table->protocol_id,
|
||||
id_table->name);
|
||||
/* Set handle if not already set: device existed */
|
||||
if (sdev && !sdev->handle)
|
||||
sdev->handle =
|
||||
scmi_handle_get_from_info_unlocked(info);
|
||||
if (sdev) {
|
||||
/* Set handle if not already set: device existed */
|
||||
if (!sdev->handle)
|
||||
sdev->handle =
|
||||
scmi_handle_get_from_info_unlocked(info);
|
||||
/* Relink consumer and suppliers */
|
||||
if (sdev->handle)
|
||||
scmi_device_link_add(&sdev->dev,
|
||||
sdev->handle->dev);
|
||||
}
|
||||
} else {
|
||||
dev_err(info->dev,
|
||||
"Failed. SCMI protocol %d not active.\n",
|
||||
@@ -1920,20 +1926,17 @@ void scmi_free_channel(struct scmi_chan_info *cinfo, struct idr *idr, int id)
|
||||
|
||||
static int scmi_remove(struct platform_device *pdev)
|
||||
{
|
||||
int ret = 0, id;
|
||||
int ret, id;
|
||||
struct scmi_info *info = platform_get_drvdata(pdev);
|
||||
struct device_node *child;
|
||||
|
||||
mutex_lock(&scmi_list_mutex);
|
||||
if (info->users)
|
||||
ret = -EBUSY;
|
||||
else
|
||||
list_del(&info->node);
|
||||
dev_warn(&pdev->dev,
|
||||
"Still active SCMI users will be forcibly unbound.\n");
|
||||
list_del(&info->node);
|
||||
mutex_unlock(&scmi_list_mutex);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
scmi_notification_exit(&info->handle);
|
||||
|
||||
mutex_lock(&info->protocols_mtx);
|
||||
@@ -1945,7 +1948,11 @@ static int scmi_remove(struct platform_device *pdev)
|
||||
idr_destroy(&info->active_protocols);
|
||||
|
||||
/* Safe to free channels since no more users */
|
||||
return scmi_cleanup_txrx_channels(info);
|
||||
ret = scmi_cleanup_txrx_channels(info);
|
||||
if (ret)
|
||||
dev_warn(&pdev->dev, "Failed to cleanup SCMI channels.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t protocol_version_show(struct device *dev,
|
||||
|
||||
@@ -149,12 +149,8 @@ static int coreboot_table_probe(struct platform_device *pdev)
|
||||
if (!ptr)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = bus_register(&coreboot_bus_type);
|
||||
if (!ret) {
|
||||
ret = coreboot_table_populate(dev, ptr);
|
||||
if (ret)
|
||||
bus_unregister(&coreboot_bus_type);
|
||||
}
|
||||
ret = coreboot_table_populate(dev, ptr);
|
||||
|
||||
memunmap(ptr);
|
||||
|
||||
return ret;
|
||||
@@ -169,7 +165,6 @@ static int __cb_dev_unregister(struct device *dev, void *dummy)
|
||||
static int coreboot_table_remove(struct platform_device *pdev)
|
||||
{
|
||||
bus_for_each_dev(&coreboot_bus_type, NULL, NULL, __cb_dev_unregister);
|
||||
bus_unregister(&coreboot_bus_type);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -199,6 +194,32 @@ static struct platform_driver coreboot_table_driver = {
|
||||
.of_match_table = of_match_ptr(coreboot_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(coreboot_table_driver);
|
||||
|
||||
static int __init coreboot_table_driver_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = bus_register(&coreboot_bus_type);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&coreboot_table_driver);
|
||||
if (ret) {
|
||||
bus_unregister(&coreboot_bus_type);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit coreboot_table_driver_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&coreboot_table_driver);
|
||||
bus_unregister(&coreboot_bus_type);
|
||||
}
|
||||
|
||||
module_init(coreboot_table_driver_init);
|
||||
module_exit(coreboot_table_driver_exit);
|
||||
|
||||
MODULE_AUTHOR("Google, Inc.");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@@ -1765,7 +1765,7 @@ void dcn20_post_unlock_program_front_end(
|
||||
|
||||
for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
|
||||
&& hubp->funcs->hubp_is_flip_pending(hubp); j++)
|
||||
mdelay(1);
|
||||
udelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -79,6 +79,7 @@ static struct hubp_funcs dcn31_hubp_funcs = {
|
||||
.hubp_init = hubp3_init,
|
||||
.set_unbounded_requesting = hubp31_set_unbounded_requesting,
|
||||
.hubp_soft_reset = hubp31_soft_reset,
|
||||
.hubp_set_flip_int = hubp1_set_flip_int,
|
||||
.hubp_in_blank = hubp1_in_blank,
|
||||
};
|
||||
|
||||
|
||||
@@ -614,7 +614,7 @@ static int drm_dev_init(struct drm_device *dev,
|
||||
mutex_init(&dev->clientlist_mutex);
|
||||
mutex_init(&dev->master_mutex);
|
||||
|
||||
ret = drmm_add_action(dev, drm_dev_init_release, NULL);
|
||||
ret = drmm_add_action_or_reset(dev, drm_dev_init_release, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
@@ -104,7 +104,8 @@ static inline void drm_vblank_flush_worker(struct drm_vblank_crtc *vblank)
|
||||
|
||||
static inline void drm_vblank_destroy_worker(struct drm_vblank_crtc *vblank)
|
||||
{
|
||||
kthread_destroy_worker(vblank->worker);
|
||||
if (vblank->worker)
|
||||
kthread_destroy_worker(vblank->worker);
|
||||
}
|
||||
|
||||
int drm_vblank_worker_init(struct drm_vblank_crtc *vblank);
|
||||
|
||||
@@ -217,8 +217,9 @@ static int imx_tve_connector_get_modes(struct drm_connector *connector)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int imx_tve_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
static enum drm_mode_status
|
||||
imx_tve_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct imx_tve *tve = con_to_tve(connector);
|
||||
unsigned long rate;
|
||||
|
||||
@@ -3090,6 +3090,7 @@ static const struct display_timing logictechno_lt161010_2nh_timing = {
|
||||
static const struct panel_desc logictechno_lt161010_2nh = {
|
||||
.timings = &logictechno_lt161010_2nh_timing,
|
||||
.num_timings = 1,
|
||||
.bpc = 6,
|
||||
.size = {
|
||||
.width = 154,
|
||||
.height = 86,
|
||||
@@ -3119,6 +3120,7 @@ static const struct display_timing logictechno_lt170410_2whc_timing = {
|
||||
static const struct panel_desc logictechno_lt170410_2whc = {
|
||||
.timings = &logictechno_lt170410_2whc_timing,
|
||||
.num_timings = 1,
|
||||
.bpc = 8,
|
||||
.size = {
|
||||
.width = 217,
|
||||
.height = 136,
|
||||
|
||||
@@ -193,8 +193,8 @@ vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
|
||||
struct drm_private_state *priv_state;
|
||||
|
||||
priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
|
||||
if (IS_ERR(priv_state))
|
||||
return ERR_CAST(priv_state);
|
||||
if (!priv_state)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
return to_vc4_hvs_state(priv_state);
|
||||
}
|
||||
@@ -206,8 +206,8 @@ vc4_hvs_get_old_global_state(struct drm_atomic_state *state)
|
||||
struct drm_private_state *priv_state;
|
||||
|
||||
priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels);
|
||||
if (IS_ERR(priv_state))
|
||||
return ERR_CAST(priv_state);
|
||||
if (!priv_state)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
return to_vc4_hvs_state(priv_state);
|
||||
}
|
||||
|
||||
@@ -1242,6 +1242,7 @@ static const struct {
|
||||
*/
|
||||
{ "Latitude 5480", 0x29 },
|
||||
{ "Vostro V131", 0x1d },
|
||||
{ "Vostro 5568", 0x29 },
|
||||
};
|
||||
|
||||
static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
|
||||
|
||||
@@ -283,6 +283,7 @@ struct tegra_i2c_dev {
|
||||
struct dma_chan *tx_dma_chan;
|
||||
struct dma_chan *rx_dma_chan;
|
||||
unsigned int dma_buf_size;
|
||||
struct device *dma_dev;
|
||||
dma_addr_t dma_phys;
|
||||
void *dma_buf;
|
||||
|
||||
@@ -419,7 +420,7 @@ static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
|
||||
static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
|
||||
{
|
||||
if (i2c_dev->dma_buf) {
|
||||
dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
|
||||
dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
|
||||
i2c_dev->dma_buf, i2c_dev->dma_phys);
|
||||
i2c_dev->dma_buf = NULL;
|
||||
}
|
||||
@@ -466,10 +467,13 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
|
||||
|
||||
i2c_dev->tx_dma_chan = chan;
|
||||
|
||||
WARN_ON(i2c_dev->tx_dma_chan->device != i2c_dev->rx_dma_chan->device);
|
||||
i2c_dev->dma_dev = chan->device->dev;
|
||||
|
||||
i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
|
||||
I2C_PACKET_HEADER_SIZE;
|
||||
|
||||
dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
|
||||
dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
|
||||
&dma_phys, GFP_KERNEL | __GFP_NOWARN);
|
||||
if (!dma_buf) {
|
||||
dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
|
||||
@@ -1255,7 +1259,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
|
||||
|
||||
if (i2c_dev->dma_mode) {
|
||||
if (i2c_dev->msg_read) {
|
||||
dma_sync_single_for_device(i2c_dev->dev,
|
||||
dma_sync_single_for_device(i2c_dev->dma_dev,
|
||||
i2c_dev->dma_phys,
|
||||
xfer_size, DMA_FROM_DEVICE);
|
||||
|
||||
@@ -1263,7 +1267,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
|
||||
if (err)
|
||||
return err;
|
||||
} else {
|
||||
dma_sync_single_for_cpu(i2c_dev->dev,
|
||||
dma_sync_single_for_cpu(i2c_dev->dma_dev,
|
||||
i2c_dev->dma_phys,
|
||||
xfer_size, DMA_TO_DEVICE);
|
||||
}
|
||||
@@ -1276,7 +1280,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
|
||||
memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
|
||||
msg->buf, msg->len);
|
||||
|
||||
dma_sync_single_for_device(i2c_dev->dev,
|
||||
dma_sync_single_for_device(i2c_dev->dma_dev,
|
||||
i2c_dev->dma_phys,
|
||||
xfer_size, DMA_TO_DEVICE);
|
||||
|
||||
@@ -1327,7 +1331,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
|
||||
}
|
||||
|
||||
if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
|
||||
dma_sync_single_for_cpu(i2c_dev->dev,
|
||||
dma_sync_single_for_cpu(i2c_dev->dma_dev,
|
||||
i2c_dev->dma_phys,
|
||||
xfer_size, DMA_FROM_DEVICE);
|
||||
|
||||
|
||||
@@ -634,8 +634,10 @@ static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
|
||||
trig->ops = &at91_adc_trigger_ops;
|
||||
|
||||
ret = iio_trigger_register(trig);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
iio_trigger_free(trig);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return trig;
|
||||
}
|
||||
|
||||
@@ -56,7 +56,8 @@ static struct iio_map mp2629_adc_maps[] = {
|
||||
MP2629_MAP(SYSTEM_VOLT, "system-volt"),
|
||||
MP2629_MAP(INPUT_VOLT, "input-volt"),
|
||||
MP2629_MAP(BATT_CURRENT, "batt-current"),
|
||||
MP2629_MAP(INPUT_CURRENT, "input-current")
|
||||
MP2629_MAP(INPUT_CURRENT, "input-current"),
|
||||
{ }
|
||||
};
|
||||
|
||||
static int mp2629_read_raw(struct iio_dev *indio_dev,
|
||||
@@ -73,7 +74,7 @@ static int mp2629_read_raw(struct iio_dev *indio_dev,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (chan->address == MP2629_INPUT_VOLT)
|
||||
if (chan->channel == MP2629_INPUT_VOLT)
|
||||
rval &= GENMASK(6, 0);
|
||||
*val = rval;
|
||||
return IIO_VAL_INT;
|
||||
|
||||
@@ -94,7 +94,7 @@ static int ms5611_spi_probe(struct spi_device *spi)
|
||||
spi_set_drvdata(spi, indio_dev);
|
||||
|
||||
spi->mode = SPI_MODE_0;
|
||||
spi->max_speed_hz = 20000000;
|
||||
spi->max_speed_hz = min(spi->max_speed_hz, 20000000U);
|
||||
spi->bits_per_word = 8;
|
||||
ret = spi_setup(spi);
|
||||
if (ret < 0)
|
||||
|
||||
@@ -208,9 +208,13 @@ static int iio_sysfs_trigger_remove(int id)
|
||||
|
||||
static int __init iio_sysfs_trig_init(void)
|
||||
{
|
||||
int ret;
|
||||
device_initialize(&iio_sysfs_trig_dev);
|
||||
dev_set_name(&iio_sysfs_trig_dev, "iio_sysfs_trigger");
|
||||
return device_add(&iio_sysfs_trig_dev);
|
||||
ret = device_add(&iio_sysfs_trig_dev);
|
||||
if (ret)
|
||||
put_device(&iio_sysfs_trig_dev);
|
||||
return ret;
|
||||
}
|
||||
module_init(iio_sysfs_trig_init);
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
|
||||
/*
|
||||
* Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
|
||||
* Copyright 2018-2022 Amazon.com, Inc. or its affiliates. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
@@ -14,10 +14,12 @@
|
||||
|
||||
#define PCI_DEV_ID_EFA0_VF 0xefa0
|
||||
#define PCI_DEV_ID_EFA1_VF 0xefa1
|
||||
#define PCI_DEV_ID_EFA2_VF 0xefa2
|
||||
|
||||
static const struct pci_device_id efa_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(AMAZON, PCI_DEV_ID_EFA0_VF) },
|
||||
{ PCI_VDEVICE(AMAZON, PCI_DEV_ID_EFA1_VF) },
|
||||
{ PCI_VDEVICE(AMAZON, PCI_DEV_ID_EFA2_VF) },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@@ -273,22 +273,22 @@ int iforce_init_device(struct device *parent, u16 bustype,
|
||||
* Get device info.
|
||||
*/
|
||||
|
||||
if (!iforce_get_id_packet(iforce, 'M', buf, &len) || len < 3)
|
||||
if (!iforce_get_id_packet(iforce, 'M', buf, &len) && len >= 3)
|
||||
input_dev->id.vendor = get_unaligned_le16(buf + 1);
|
||||
else
|
||||
dev_warn(&iforce->dev->dev, "Device does not respond to id packet M\n");
|
||||
|
||||
if (!iforce_get_id_packet(iforce, 'P', buf, &len) || len < 3)
|
||||
if (!iforce_get_id_packet(iforce, 'P', buf, &len) && len >= 3)
|
||||
input_dev->id.product = get_unaligned_le16(buf + 1);
|
||||
else
|
||||
dev_warn(&iforce->dev->dev, "Device does not respond to id packet P\n");
|
||||
|
||||
if (!iforce_get_id_packet(iforce, 'B', buf, &len) || len < 3)
|
||||
if (!iforce_get_id_packet(iforce, 'B', buf, &len) && len >= 3)
|
||||
iforce->device_memory.end = get_unaligned_le16(buf + 1);
|
||||
else
|
||||
dev_warn(&iforce->dev->dev, "Device does not respond to id packet B\n");
|
||||
|
||||
if (!iforce_get_id_packet(iforce, 'N', buf, &len) || len < 2)
|
||||
if (!iforce_get_id_packet(iforce, 'N', buf, &len) && len >= 2)
|
||||
ff_effects = buf[1];
|
||||
else
|
||||
dev_warn(&iforce->dev->dev, "Device does not respond to id packet N\n");
|
||||
|
||||
@@ -1543,8 +1543,6 @@ static int i8042_probe(struct platform_device *dev)
|
||||
{
|
||||
int error;
|
||||
|
||||
i8042_platform_device = dev;
|
||||
|
||||
if (i8042_reset == I8042_RESET_ALWAYS) {
|
||||
error = i8042_controller_selftest();
|
||||
if (error)
|
||||
@@ -1582,7 +1580,6 @@ static int i8042_probe(struct platform_device *dev)
|
||||
i8042_free_aux_ports(); /* in case KBD failed but AUX not */
|
||||
i8042_free_irqs();
|
||||
i8042_controller_reset(false);
|
||||
i8042_platform_device = NULL;
|
||||
|
||||
return error;
|
||||
}
|
||||
@@ -1592,7 +1589,6 @@ static int i8042_remove(struct platform_device *dev)
|
||||
i8042_unregister_ports();
|
||||
i8042_free_irqs();
|
||||
i8042_controller_reset(false);
|
||||
i8042_platform_device = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1048,11 +1048,9 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
|
||||
|
||||
domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
|
||||
pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
|
||||
if (domain_use_first_level(domain)) {
|
||||
pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
|
||||
if (iommu_is_dma_domain(&domain->domain))
|
||||
pteval |= DMA_FL_PTE_ACCESS;
|
||||
}
|
||||
if (domain_use_first_level(domain))
|
||||
pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;
|
||||
|
||||
if (cmpxchg64(&pte->val, 0ULL, pteval))
|
||||
/* Someone else set it while we were thinking; use theirs. */
|
||||
free_pgtable_page(tmp_page);
|
||||
|
||||
@@ -717,7 +717,7 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
|
||||
* Since it is a second level only translation setup, we should
|
||||
* set SRE bit as well (addresses are expected to be GPAs).
|
||||
*/
|
||||
if (pasid != PASID_RID2PASID)
|
||||
if (pasid != PASID_RID2PASID && ecap_srs(iommu->ecap))
|
||||
pasid_set_sre(pte);
|
||||
pasid_set_present(pte);
|
||||
pasid_flush_caches(iommu, pte, pasid, did);
|
||||
@@ -756,7 +756,8 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
|
||||
* We should set SRE bit as well since the addresses are expected
|
||||
* to be GPAs.
|
||||
*/
|
||||
pasid_set_sre(pte);
|
||||
if (ecap_srs(iommu->ecap))
|
||||
pasid_set_sre(pte);
|
||||
pasid_set_present(pte);
|
||||
pasid_flush_caches(iommu, pte, pasid, did);
|
||||
|
||||
|
||||
@@ -222,7 +222,7 @@ mISDN_register_device(struct mISDNdevice *dev,
|
||||
|
||||
err = get_free_devid();
|
||||
if (err < 0)
|
||||
goto error1;
|
||||
return err;
|
||||
dev->id = err;
|
||||
|
||||
device_initialize(&dev->dev);
|
||||
|
||||
@@ -77,6 +77,7 @@ int mISDN_dsp_element_register(struct mISDN_dsp_element *elem)
|
||||
if (!entry)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_LIST_HEAD(&entry->list);
|
||||
entry->elem = elem;
|
||||
|
||||
entry->dev.class = elements_class;
|
||||
@@ -107,7 +108,7 @@ err2:
|
||||
device_unregister(&entry->dev);
|
||||
return ret;
|
||||
err1:
|
||||
kfree(entry);
|
||||
put_device(&entry->dev);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(mISDN_dsp_element_register);
|
||||
|
||||
@@ -655,7 +655,7 @@ static void list_version_get_needed(struct target_type *tt, void *needed_param)
|
||||
size_t *needed = needed_param;
|
||||
|
||||
*needed += sizeof(struct dm_target_versions);
|
||||
*needed += strlen(tt->name);
|
||||
*needed += strlen(tt->name) + 1;
|
||||
*needed += ALIGN_MASK;
|
||||
}
|
||||
|
||||
@@ -720,7 +720,7 @@ static int __list_versions(struct dm_ioctl *param, size_t param_size, const char
|
||||
iter_info.old_vers = NULL;
|
||||
iter_info.vers = vers;
|
||||
iter_info.flags = 0;
|
||||
iter_info.end = (char *)vers+len;
|
||||
iter_info.end = (char *)vers + needed;
|
||||
|
||||
/*
|
||||
* Now loop through filling out the names & versions.
|
||||
|
||||
@@ -63,6 +63,8 @@
|
||||
#define SPIBASE_BYT 0x54
|
||||
#define SPIBASE_BYT_SZ 512
|
||||
#define SPIBASE_BYT_EN BIT(1)
|
||||
#define BYT_BCR 0xfc
|
||||
#define BYT_BCR_WPD BIT(0)
|
||||
|
||||
#define SPIBASE_LPT 0x3800
|
||||
#define SPIBASE_LPT_SZ 512
|
||||
@@ -1084,12 +1086,57 @@ wdt_done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(base + BYT_BCR);
|
||||
if (!(val & BYT_BCR_WPD)) {
|
||||
val |= BYT_BCR_WPD;
|
||||
writel(val, base + BYT_BCR);
|
||||
val = readl(base + BYT_BCR);
|
||||
}
|
||||
|
||||
return val & BYT_BCR_WPD;
|
||||
}
|
||||
|
||||
static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
|
||||
{
|
||||
struct pci_dev *pdev = data;
|
||||
u32 bcr;
|
||||
|
||||
pci_read_config_dword(pdev, BCR, &bcr);
|
||||
if (!(bcr & BCR_WPD)) {
|
||||
bcr |= BCR_WPD;
|
||||
pci_write_config_dword(pdev, BCR, bcr);
|
||||
pci_read_config_dword(pdev, BCR, &bcr);
|
||||
}
|
||||
|
||||
return bcr & BCR_WPD;
|
||||
}
|
||||
|
||||
static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
|
||||
{
|
||||
unsigned int spi = PCI_DEVFN(13, 2);
|
||||
struct pci_bus *bus = data;
|
||||
u32 bcr;
|
||||
|
||||
pci_bus_read_config_dword(bus, spi, BCR, &bcr);
|
||||
if (!(bcr & BCR_WPD)) {
|
||||
bcr |= BCR_WPD;
|
||||
pci_bus_write_config_dword(bus, spi, BCR, bcr);
|
||||
pci_bus_read_config_dword(bus, spi, BCR, &bcr);
|
||||
}
|
||||
|
||||
return bcr & BCR_WPD;
|
||||
}
|
||||
|
||||
static int lpc_ich_init_spi(struct pci_dev *dev)
|
||||
{
|
||||
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
|
||||
struct resource *res = &intel_spi_res[0];
|
||||
struct intel_spi_boardinfo *info;
|
||||
u32 spi_base, rcba, bcr;
|
||||
u32 spi_base, rcba;
|
||||
|
||||
info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
|
||||
if (!info)
|
||||
@@ -1103,6 +1150,8 @@ static int lpc_ich_init_spi(struct pci_dev *dev)
|
||||
if (spi_base & SPIBASE_BYT_EN) {
|
||||
res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
|
||||
res->end = res->start + SPIBASE_BYT_SZ - 1;
|
||||
|
||||
info->set_writeable = lpc_ich_byt_set_writeable;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -1113,8 +1162,8 @@ static int lpc_ich_init_spi(struct pci_dev *dev)
|
||||
res->start = spi_base + SPIBASE_LPT;
|
||||
res->end = res->start + SPIBASE_LPT_SZ - 1;
|
||||
|
||||
pci_read_config_dword(dev, BCR, &bcr);
|
||||
info->writeable = !!(bcr & BCR_WPD);
|
||||
info->set_writeable = lpc_ich_lpt_set_writeable;
|
||||
info->data = dev;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -1135,8 +1184,8 @@ static int lpc_ich_init_spi(struct pci_dev *dev)
|
||||
res->start = spi_base & 0xfffffff0;
|
||||
res->end = res->start + SPIBASE_APL_SZ - 1;
|
||||
|
||||
pci_bus_read_config_dword(bus, spi, BCR, &bcr);
|
||||
info->writeable = !!(bcr & BCR_WPD);
|
||||
info->set_writeable = lpc_ich_bxt_set_writeable;
|
||||
info->data = bus;
|
||||
}
|
||||
|
||||
pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
|
||||
|
||||
@@ -854,6 +854,7 @@ static int qp_notify_peer_local(bool attach, struct vmci_handle handle)
|
||||
u32 context_id = vmci_get_context_id();
|
||||
struct vmci_event_qp ev;
|
||||
|
||||
memset(&ev, 0, sizeof(ev));
|
||||
ev.msg.hdr.dst = vmci_make_handle(context_id, VMCI_EVENT_HANDLER);
|
||||
ev.msg.hdr.src = vmci_make_handle(VMCI_HYPERVISOR_CONTEXT_ID,
|
||||
VMCI_CONTEXT_RESOURCE_ID);
|
||||
@@ -1467,6 +1468,7 @@ static int qp_notify_peer(bool attach,
|
||||
* kernel.
|
||||
*/
|
||||
|
||||
memset(&ev, 0, sizeof(ev));
|
||||
ev.msg.hdr.dst = vmci_make_handle(peer_id, VMCI_EVENT_HANDLER);
|
||||
ev.msg.hdr.src = vmci_make_handle(VMCI_HYPERVISOR_CONTEXT_ID,
|
||||
VMCI_CONTEXT_RESOURCE_ID);
|
||||
|
||||
@@ -1139,7 +1139,13 @@ u32 mmc_select_voltage(struct mmc_host *host, u32 ocr)
|
||||
mmc_power_cycle(host, ocr);
|
||||
} else {
|
||||
bit = fls(ocr) - 1;
|
||||
ocr &= 3 << bit;
|
||||
/*
|
||||
* The bit variable represents the highest voltage bit set in
|
||||
* the OCR register.
|
||||
* To keep a range of 2 values (e.g. 3.2V/3.3V and 3.3V/3.4V),
|
||||
* we must shift the mask '3' with (bit - 1).
|
||||
*/
|
||||
ocr &= 3 << (bit - 1);
|
||||
if (bit != host->ios.vdd)
|
||||
dev_warn(mmc_dev(host), "exceeding card's volts\n");
|
||||
}
|
||||
|
||||
@@ -1818,6 +1818,8 @@ static int amd_probe(struct sdhci_pci_chip *chip)
|
||||
}
|
||||
}
|
||||
|
||||
pci_dev_put(smbus_dev);
|
||||
|
||||
if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
|
||||
chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
|
||||
|
||||
|
||||
@@ -31,6 +31,7 @@
|
||||
#define O2_SD_CAPS 0xE0
|
||||
#define O2_SD_ADMA1 0xE2
|
||||
#define O2_SD_ADMA2 0xE7
|
||||
#define O2_SD_MISC_CTRL2 0xF0
|
||||
#define O2_SD_INF_MOD 0xF1
|
||||
#define O2_SD_MISC_CTRL4 0xFC
|
||||
#define O2_SD_MISC_CTRL 0x1C0
|
||||
@@ -830,6 +831,12 @@ static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
|
||||
/* Set Tuning Windows to 5 */
|
||||
pci_write_config_byte(chip->pdev,
|
||||
O2_SD_TUNING_CTRL, 0x55);
|
||||
//Adjust 1st and 2nd CD debounce time
|
||||
pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
|
||||
scratch_32 &= 0xFFE7FFFF;
|
||||
scratch_32 |= 0x00180000;
|
||||
pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
|
||||
pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1);
|
||||
/* Lock WP */
|
||||
ret = pci_read_config_byte(chip->pdev,
|
||||
O2_SD_LOCK_WP, &scratch);
|
||||
|
||||
@@ -16,12 +16,30 @@
|
||||
#define BCR 0xdc
|
||||
#define BCR_WPD BIT(0)
|
||||
|
||||
static bool intel_spi_pci_set_writeable(void __iomem *base, void *data)
|
||||
{
|
||||
struct pci_dev *pdev = data;
|
||||
u32 bcr;
|
||||
|
||||
/* Try to make the chip read/write */
|
||||
pci_read_config_dword(pdev, BCR, &bcr);
|
||||
if (!(bcr & BCR_WPD)) {
|
||||
bcr |= BCR_WPD;
|
||||
pci_write_config_dword(pdev, BCR, bcr);
|
||||
pci_read_config_dword(pdev, BCR, &bcr);
|
||||
}
|
||||
|
||||
return bcr & BCR_WPD;
|
||||
}
|
||||
|
||||
static const struct intel_spi_boardinfo bxt_info = {
|
||||
.type = INTEL_SPI_BXT,
|
||||
.set_writeable = intel_spi_pci_set_writeable,
|
||||
};
|
||||
|
||||
static const struct intel_spi_boardinfo cnl_info = {
|
||||
.type = INTEL_SPI_CNL,
|
||||
.set_writeable = intel_spi_pci_set_writeable,
|
||||
};
|
||||
|
||||
static int intel_spi_pci_probe(struct pci_dev *pdev,
|
||||
@@ -29,7 +47,6 @@ static int intel_spi_pci_probe(struct pci_dev *pdev,
|
||||
{
|
||||
struct intel_spi_boardinfo *info;
|
||||
struct intel_spi *ispi;
|
||||
u32 bcr;
|
||||
int ret;
|
||||
|
||||
ret = pcim_enable_device(pdev);
|
||||
@@ -41,15 +58,7 @@ static int intel_spi_pci_probe(struct pci_dev *pdev,
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Try to make the chip read/write */
|
||||
pci_read_config_dword(pdev, BCR, &bcr);
|
||||
if (!(bcr & BCR_WPD)) {
|
||||
bcr |= BCR_WPD;
|
||||
pci_write_config_dword(pdev, BCR, bcr);
|
||||
pci_read_config_dword(pdev, BCR, &bcr);
|
||||
}
|
||||
info->writeable = !!(bcr & BCR_WPD);
|
||||
|
||||
info->data = pdev;
|
||||
ispi = intel_spi_probe(&pdev->dev, &pdev->resource[0], info);
|
||||
if (IS_ERR(ispi))
|
||||
return PTR_ERR(ispi);
|
||||
|
||||
@@ -52,17 +52,17 @@
|
||||
#define FRACC 0x50
|
||||
|
||||
#define FREG(n) (0x54 + ((n) * 4))
|
||||
#define FREG_BASE_MASK 0x3fff
|
||||
#define FREG_BASE_MASK GENMASK(14, 0)
|
||||
#define FREG_LIMIT_SHIFT 16
|
||||
#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
|
||||
#define FREG_LIMIT_MASK GENMASK(30, 16)
|
||||
|
||||
/* Offset is from @ispi->pregs */
|
||||
#define PR(n) ((n) * 4)
|
||||
#define PR_WPE BIT(31)
|
||||
#define PR_LIMIT_SHIFT 16
|
||||
#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
|
||||
#define PR_LIMIT_MASK GENMASK(30, 16)
|
||||
#define PR_RPE BIT(15)
|
||||
#define PR_BASE_MASK 0x3fff
|
||||
#define PR_BASE_MASK GENMASK(14, 0)
|
||||
|
||||
/* Offsets are from @ispi->sregs */
|
||||
#define SSFSTS_CTL 0x00
|
||||
@@ -116,7 +116,7 @@
|
||||
#define ERASE_OPCODE_SHIFT 8
|
||||
#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
|
||||
#define ERASE_64K_OPCODE_SHIFT 16
|
||||
#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
|
||||
#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)
|
||||
|
||||
#define INTEL_SPI_TIMEOUT 5000 /* ms */
|
||||
#define INTEL_SPI_FIFO_SZ 64
|
||||
@@ -131,7 +131,6 @@
|
||||
* @sregs: Start of software sequencer registers
|
||||
* @nregions: Maximum number of regions
|
||||
* @pr_num: Maximum number of protected range registers
|
||||
* @writeable: Is the chip writeable
|
||||
* @locked: Is SPI setting locked
|
||||
* @swseq_reg: Use SW sequencer in register reads/writes
|
||||
* @swseq_erase: Use SW sequencer in erase operation
|
||||
@@ -149,7 +148,6 @@ struct intel_spi {
|
||||
void __iomem *sregs;
|
||||
size_t nregions;
|
||||
size_t pr_num;
|
||||
bool writeable;
|
||||
bool locked;
|
||||
bool swseq_reg;
|
||||
bool swseq_erase;
|
||||
@@ -304,6 +302,14 @@ static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
|
||||
INTEL_SPI_TIMEOUT * 1000);
|
||||
}
|
||||
|
||||
static bool intel_spi_set_writeable(struct intel_spi *ispi)
|
||||
{
|
||||
if (!ispi->info->set_writeable)
|
||||
return false;
|
||||
|
||||
return ispi->info->set_writeable(ispi->base, ispi->info->data);
|
||||
}
|
||||
|
||||
static int intel_spi_init(struct intel_spi *ispi)
|
||||
{
|
||||
u32 opmenu0, opmenu1, lvscc, uvscc, val;
|
||||
@@ -316,19 +322,6 @@ static int intel_spi_init(struct intel_spi *ispi)
|
||||
ispi->nregions = BYT_FREG_NUM;
|
||||
ispi->pr_num = BYT_PR_NUM;
|
||||
ispi->swseq_reg = true;
|
||||
|
||||
if (writeable) {
|
||||
/* Disable write protection */
|
||||
val = readl(ispi->base + BYT_BCR);
|
||||
if (!(val & BYT_BCR_WPD)) {
|
||||
val |= BYT_BCR_WPD;
|
||||
writel(val, ispi->base + BYT_BCR);
|
||||
val = readl(ispi->base + BYT_BCR);
|
||||
}
|
||||
|
||||
ispi->writeable = !!(val & BYT_BCR_WPD);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case INTEL_SPI_LPT:
|
||||
@@ -358,6 +351,12 @@ static int intel_spi_init(struct intel_spi *ispi)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Try to disable write protection if user asked to do so */
|
||||
if (writeable && !intel_spi_set_writeable(ispi)) {
|
||||
dev_warn(ispi->dev, "can't disable chip write protection\n");
|
||||
writeable = false;
|
||||
}
|
||||
|
||||
/* Disable #SMI generation from HW sequencer */
|
||||
val = readl(ispi->base + HSFSTS_CTL);
|
||||
val &= ~HSFSTS_CTL_FSMIE;
|
||||
@@ -884,9 +883,12 @@ static void intel_spi_fill_partition(struct intel_spi *ispi,
|
||||
/*
|
||||
* If any of the regions have protection bits set, make the
|
||||
* whole partition read-only to be on the safe side.
|
||||
*
|
||||
* Also if the user did not ask the chip to be writeable
|
||||
* mask the bit too.
|
||||
*/
|
||||
if (intel_spi_is_protected(ispi, base, limit))
|
||||
ispi->writeable = false;
|
||||
if (!writeable || intel_spi_is_protected(ispi, base, limit))
|
||||
part->mask_flags |= MTD_WRITEABLE;
|
||||
|
||||
end = (limit << 12) + 4096;
|
||||
if (end > part->size)
|
||||
@@ -927,7 +929,6 @@ struct intel_spi *intel_spi_probe(struct device *dev,
|
||||
|
||||
ispi->dev = dev;
|
||||
ispi->info = info;
|
||||
ispi->writeable = info->writeable;
|
||||
|
||||
ret = intel_spi_init(ispi);
|
||||
if (ret)
|
||||
@@ -945,10 +946,6 @@ struct intel_spi *intel_spi_probe(struct device *dev,
|
||||
|
||||
intel_spi_fill_partition(ispi, &part);
|
||||
|
||||
/* Prevent writes if not explicitly enabled */
|
||||
if (!ispi->writeable || !writeable)
|
||||
ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
|
||||
|
||||
ret = mtd_device_register(&ispi->nor.mtd, &part, 1);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
@@ -4583,13 +4583,19 @@ static struct pci_driver ena_pci_driver = {
|
||||
|
||||
static int __init ena_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
|
||||
if (!ena_wq) {
|
||||
pr_err("Failed to create workqueue\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return pci_register_driver(&ena_pci_driver);
|
||||
ret = pci_register_driver(&ena_pci_driver);
|
||||
if (ret)
|
||||
destroy_workqueue(ena_wq);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit ena_cleanup(void)
|
||||
|
||||
@@ -1480,7 +1480,7 @@ static int ag71xx_open(struct net_device *ndev)
|
||||
if (ret) {
|
||||
netif_err(ag, link, ndev, "phylink_of_phy_connect filed with err: %i\n",
|
||||
ret);
|
||||
goto err;
|
||||
return ret;
|
||||
}
|
||||
|
||||
max_frame_len = ag71xx_max_frame_len(ndev->mtu);
|
||||
@@ -1501,6 +1501,7 @@ static int ag71xx_open(struct net_device *ndev)
|
||||
|
||||
err:
|
||||
ag71xx_rings_cleanup(ag);
|
||||
phylink_disconnect_phy(ag->phylink);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@@ -1568,7 +1568,6 @@ void bgmac_enet_remove(struct bgmac *bgmac)
|
||||
phy_disconnect(bgmac->net_dev->phydev);
|
||||
netif_napi_del(&bgmac->napi);
|
||||
bgmac_dma_free(bgmac);
|
||||
free_netdev(bgmac->net_dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bgmac_enet_remove);
|
||||
|
||||
|
||||
@@ -13697,8 +13697,16 @@ static struct pci_driver bnxt_pci_driver = {
|
||||
|
||||
static int __init bnxt_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
bnxt_debug_init();
|
||||
return pci_register_driver(&bnxt_pci_driver);
|
||||
err = pci_register_driver(&bnxt_pci_driver);
|
||||
if (err) {
|
||||
bnxt_debug_exit();
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit bnxt_exit(void)
|
||||
|
||||
@@ -1798,13 +1798,10 @@ static int liquidio_open(struct net_device *netdev)
|
||||
|
||||
ifstate_set(lio, LIO_IFSTATE_RUNNING);
|
||||
|
||||
if (OCTEON_CN23XX_PF(oct)) {
|
||||
if (!oct->msix_on)
|
||||
if (setup_tx_poll_fn(netdev))
|
||||
return -1;
|
||||
} else {
|
||||
if (setup_tx_poll_fn(netdev))
|
||||
return -1;
|
||||
if (!OCTEON_CN23XX_PF(oct) || (OCTEON_CN23XX_PF(oct) && !oct->msix_on)) {
|
||||
ret = setup_tx_poll_fn(netdev);
|
||||
if (ret)
|
||||
goto err_poll;
|
||||
}
|
||||
|
||||
netif_tx_start_all_queues(netdev);
|
||||
@@ -1817,7 +1814,7 @@ static int liquidio_open(struct net_device *netdev)
|
||||
/* tell Octeon to start forwarding packets to host */
|
||||
ret = send_rx_ctrl_cmd(lio, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto err_rx_ctrl;
|
||||
|
||||
/* start periodical statistics fetch */
|
||||
INIT_DELAYED_WORK(&lio->stats_wk.work, lio_fetch_stats);
|
||||
@@ -1828,6 +1825,27 @@ static int liquidio_open(struct net_device *netdev)
|
||||
dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
|
||||
netdev->name);
|
||||
|
||||
return 0;
|
||||
|
||||
err_rx_ctrl:
|
||||
if (!OCTEON_CN23XX_PF(oct) || (OCTEON_CN23XX_PF(oct) && !oct->msix_on))
|
||||
cleanup_tx_poll_fn(netdev);
|
||||
err_poll:
|
||||
if (lio->ptp_clock) {
|
||||
ptp_clock_unregister(lio->ptp_clock);
|
||||
lio->ptp_clock = NULL;
|
||||
}
|
||||
|
||||
if (oct->props[lio->ifidx].napi_enabled == 1) {
|
||||
list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
|
||||
napi_disable(napi);
|
||||
|
||||
oct->props[lio->ifidx].napi_enabled = 0;
|
||||
|
||||
if (OCTEON_CN23XX_PF(oct))
|
||||
oct->droq[0]->ops.poll_mode = 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@@ -3172,6 +3172,7 @@ static int hclge_update_tp_port_info(struct hclge_dev *hdev)
|
||||
hdev->hw.mac.autoneg = cmd.base.autoneg;
|
||||
hdev->hw.mac.speed = cmd.base.speed;
|
||||
hdev->hw.mac.duplex = cmd.base.duplex;
|
||||
linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -11669,9 +11670,12 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
|
||||
if (ret)
|
||||
goto err_msi_irq_uninit;
|
||||
|
||||
if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER &&
|
||||
!hnae3_dev_phy_imp_supported(hdev)) {
|
||||
ret = hclge_mac_mdio_config(hdev);
|
||||
if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
|
||||
if (hnae3_dev_phy_imp_supported(hdev))
|
||||
ret = hclge_update_tp_port_info(hdev);
|
||||
else
|
||||
ret = hclge_mac_mdio_config(hdev);
|
||||
|
||||
if (ret)
|
||||
goto err_msi_irq_uninit;
|
||||
}
|
||||
|
||||
@@ -1482,8 +1482,15 @@ static struct pci_driver hinic_driver = {
|
||||
|
||||
static int __init hinic_module_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
hinic_dbg_register_debugfs(HINIC_DRV_NAME);
|
||||
return pci_register_driver(&hinic_driver);
|
||||
|
||||
ret = pci_register_driver(&hinic_driver);
|
||||
if (ret)
|
||||
hinic_dbg_unregister_debugfs();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit hinic_module_exit(void)
|
||||
|
||||
@@ -1219,6 +1219,9 @@ int sparx_stats_init(struct sparx5 *sparx5)
|
||||
snprintf(queue_name, sizeof(queue_name), "%s-stats",
|
||||
dev_name(sparx5->dev));
|
||||
sparx5->stats_queue = create_singlethread_workqueue(queue_name);
|
||||
if (!sparx5->stats_queue)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_DELAYED_WORK(&sparx5->stats_work, sparx5_check_stats_work);
|
||||
queue_delayed_work(sparx5->stats_queue, &sparx5->stats_work,
|
||||
SPX5_STATS_CHECK_DELAY);
|
||||
|
||||
@@ -629,6 +629,9 @@ static int sparx5_start(struct sparx5 *sparx5)
|
||||
snprintf(queue_name, sizeof(queue_name), "%s-mact",
|
||||
dev_name(sparx5->dev));
|
||||
sparx5->mact_queue = create_singlethread_workqueue(queue_name);
|
||||
if (!sparx5->mact_queue)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work);
|
||||
queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work,
|
||||
SPX5_MACT_PULL_DELAY);
|
||||
|
||||
@@ -1264,15 +1264,15 @@ nfp_port_get_module_info(struct net_device *netdev,
|
||||
|
||||
if (data < 0x3) {
|
||||
modinfo->type = ETH_MODULE_SFF_8436;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
|
||||
} else {
|
||||
modinfo->type = ETH_MODULE_SFF_8636;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
|
||||
}
|
||||
break;
|
||||
case NFP_INTERFACE_QSFP28:
|
||||
modinfo->type = ETH_MODULE_SFF_8636;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
|
||||
modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
|
||||
break;
|
||||
default:
|
||||
netdev_err(netdev, "Unsupported module 0x%x detected\n",
|
||||
|
||||
@@ -588,8 +588,14 @@ int ionic_port_reset(struct ionic *ionic)
|
||||
|
||||
static int __init ionic_init_module(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ionic_debugfs_create();
|
||||
return ionic_bus_register_driver();
|
||||
ret = ionic_bus_register_driver();
|
||||
if (ret)
|
||||
ionic_debugfs_destroy();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit ionic_cleanup_module(void)
|
||||
|
||||
@@ -6494,6 +6494,9 @@ void stmmac_xdp_release(struct net_device *dev)
|
||||
struct stmmac_priv *priv = netdev_priv(dev);
|
||||
u32 chan;
|
||||
|
||||
/* Ensure tx function is not running */
|
||||
netif_tx_disable(dev);
|
||||
|
||||
/* Disable NAPI process */
|
||||
stmmac_disable_all_queues(priv);
|
||||
|
||||
|
||||
@@ -141,7 +141,7 @@ static struct macvlan_source_entry *macvlan_hash_lookup_source(
|
||||
u32 idx = macvlan_eth_hash(addr);
|
||||
struct hlist_head *h = &vlan->port->vlan_source_hash[idx];
|
||||
|
||||
hlist_for_each_entry_rcu(entry, h, hlist) {
|
||||
hlist_for_each_entry_rcu(entry, h, hlist, lockdep_rtnl_is_held()) {
|
||||
if (ether_addr_equal_64bits(entry->addr, addr) &&
|
||||
entry->vlan == vlan)
|
||||
return entry;
|
||||
@@ -1181,7 +1181,7 @@ void macvlan_common_setup(struct net_device *dev)
|
||||
{
|
||||
ether_setup(dev);
|
||||
|
||||
dev->min_mtu = 0;
|
||||
/* ether_setup() has set dev->min_mtu to ETH_MIN_MTU. */
|
||||
dev->max_mtu = ETH_MAX_MTU;
|
||||
dev->priv_flags &= ~IFF_TX_SKB_SHARING;
|
||||
netif_keep_dst(dev);
|
||||
@@ -1635,7 +1635,7 @@ static int macvlan_fill_info_macaddr(struct sk_buff *skb,
|
||||
struct hlist_head *h = &vlan->port->vlan_source_hash[i];
|
||||
struct macvlan_source_entry *entry;
|
||||
|
||||
hlist_for_each_entry_rcu(entry, h, hlist) {
|
||||
hlist_for_each_entry_rcu(entry, h, hlist, lockdep_rtnl_is_held()) {
|
||||
if (entry->vlan != vlan)
|
||||
continue;
|
||||
if (nla_put(skb, IFLA_MACVLAN_MACADDR, ETH_ALEN, entry->addr))
|
||||
|
||||
@@ -343,6 +343,8 @@ static void mhi_net_dellink(struct mhi_device *mhi_dev, struct net_device *ndev)
|
||||
|
||||
kfree_skb(mhi_netdev->skbagg_head);
|
||||
|
||||
free_netdev(ndev);
|
||||
|
||||
dev_set_drvdata(&mhi_dev->dev, NULL);
|
||||
}
|
||||
|
||||
|
||||
@@ -1976,14 +1976,16 @@ static int m88e1510_loopback(struct phy_device *phydev, bool enable)
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/* FIXME: Based on trial and error test, it seem 1G need to have
|
||||
* delay between soft reset and loopback enablement.
|
||||
*/
|
||||
if (phydev->speed == SPEED_1000)
|
||||
msleep(1000);
|
||||
err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
|
||||
BMCR_LOOPBACK);
|
||||
|
||||
return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
|
||||
BMCR_LOOPBACK);
|
||||
if (!err) {
|
||||
/* It takes some time for PHY device to switch
|
||||
* into/out-of loopback mode.
|
||||
*/
|
||||
msleep(1000);
|
||||
}
|
||||
return err;
|
||||
} else {
|
||||
err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
|
||||
if (err < 0)
|
||||
|
||||
@@ -1377,12 +1377,21 @@ static int __init tbnet_init(void)
|
||||
TBNET_MATCH_FRAGS_ID | TBNET_64K_FRAMES);
|
||||
|
||||
ret = tb_register_property_dir("network", tbnet_dir);
|
||||
if (ret) {
|
||||
tb_property_free_dir(tbnet_dir);
|
||||
return ret;
|
||||
}
|
||||
if (ret)
|
||||
goto err_free_dir;
|
||||
|
||||
return tb_register_service_driver(&tbnet_driver);
|
||||
ret = tb_register_service_driver(&tbnet_driver);
|
||||
if (ret)
|
||||
goto err_unregister;
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister:
|
||||
tb_unregister_property_dir("network", tbnet_dir);
|
||||
err_free_dir:
|
||||
tb_property_free_dir(tbnet_dir);
|
||||
|
||||
return ret;
|
||||
}
|
||||
module_init(tbnet_init);
|
||||
|
||||
|
||||
@@ -484,11 +484,17 @@ long nvme_dev_ioctl(struct file *file, unsigned int cmd,
|
||||
case NVME_IOCTL_IO_CMD:
|
||||
return nvme_dev_user_cmd(ctrl, argp);
|
||||
case NVME_IOCTL_RESET:
|
||||
if (!capable(CAP_SYS_ADMIN))
|
||||
return -EACCES;
|
||||
dev_warn(ctrl->device, "resetting controller\n");
|
||||
return nvme_reset_ctrl_sync(ctrl);
|
||||
case NVME_IOCTL_SUBSYS_RESET:
|
||||
if (!capable(CAP_SYS_ADMIN))
|
||||
return -EACCES;
|
||||
return nvme_reset_subsystem(ctrl);
|
||||
case NVME_IOCTL_RESCAN:
|
||||
if (!capable(CAP_SYS_ADMIN))
|
||||
return -EACCES;
|
||||
nvme_queue_scan(ctrl);
|
||||
return 0;
|
||||
default:
|
||||
|
||||
@@ -558,11 +558,23 @@ static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj)
|
||||
static inline void nvme_should_fail(struct request *req) {}
|
||||
#endif
|
||||
|
||||
bool nvme_wait_reset(struct nvme_ctrl *ctrl);
|
||||
int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
|
||||
|
||||
static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!ctrl->subsystem)
|
||||
return -ENOTTY;
|
||||
return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
|
||||
if (!nvme_wait_reset(ctrl))
|
||||
return -EBUSY;
|
||||
|
||||
ret = ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return nvme_try_sched_reset(ctrl);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -650,7 +662,6 @@ void nvme_cancel_tagset(struct nvme_ctrl *ctrl);
|
||||
void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl);
|
||||
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
|
||||
enum nvme_ctrl_state new_state);
|
||||
bool nvme_wait_reset(struct nvme_ctrl *ctrl);
|
||||
int nvme_disable_ctrl(struct nvme_ctrl *ctrl);
|
||||
int nvme_enable_ctrl(struct nvme_ctrl *ctrl);
|
||||
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
|
||||
@@ -734,7 +745,6 @@ int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
|
||||
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
|
||||
int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
|
||||
int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
|
||||
int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
|
||||
int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
|
||||
void nvme_queue_scan(struct nvme_ctrl *ctrl);
|
||||
int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
|
||||
|
||||
@@ -468,7 +468,7 @@ static size_t parport_pc_fifo_write_block_pio(struct parport *port,
|
||||
const unsigned char *bufp = buf;
|
||||
size_t left = length;
|
||||
unsigned long expire = jiffies + port->physport->cad->timeout;
|
||||
const int fifo = FIFO(port);
|
||||
const unsigned long fifo = FIFO(port);
|
||||
int poll_for = 8; /* 80 usecs */
|
||||
const struct parport_pc_private *priv = port->physport->private_data;
|
||||
const int fifo_depth = priv->fifo_depth;
|
||||
|
||||
@@ -220,6 +220,8 @@ int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev)
|
||||
for (state = 0; ; state++) {
|
||||
/* Retrieve the pinctrl-* property */
|
||||
propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
|
||||
if (!propname)
|
||||
return -ENOMEM;
|
||||
prop = of_find_property(np, propname, &size);
|
||||
kfree(propname);
|
||||
if (!prop) {
|
||||
|
||||
@@ -608,14 +608,54 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
|
||||
}
|
||||
|
||||
static struct rockchip_mux_route_data px30_mux_route_data[] = {
|
||||
RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
|
||||
RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
|
||||
RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
|
||||
RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
|
||||
RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
|
||||
RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
|
||||
RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
|
||||
RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
|
||||
RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
|
||||
RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
|
||||
RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
|
||||
RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
|
||||
RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
|
||||
RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
|
||||
};
|
||||
|
||||
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
|
||||
|
||||
@@ -1596,16 +1596,32 @@ static void ssh_ptl_timeout_reap(struct work_struct *work)
|
||||
ssh_ptl_tx_wakeup_packet(ptl);
|
||||
}
|
||||
|
||||
static bool ssh_ptl_rx_retransmit_check(struct ssh_ptl *ptl, u8 seq)
|
||||
static bool ssh_ptl_rx_retransmit_check(struct ssh_ptl *ptl, const struct ssh_frame *frame)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Ignore unsequenced packets. On some devices (notably Surface Pro 9),
|
||||
* unsequenced events will always be sent with SEQ=0x00. Attempting to
|
||||
* detect retransmission would thus just block all events.
|
||||
*
|
||||
* While sequence numbers would also allow detection of retransmitted
|
||||
* packets in unsequenced communication, they have only ever been used
|
||||
* to cover edge-cases in sequenced transmission. In particular, the
|
||||
* only instance of packets being retransmitted (that we are aware of)
|
||||
* is due to an ACK timeout. As this does not happen in unsequenced
|
||||
* communication, skip the retransmission check for those packets
|
||||
* entirely.
|
||||
*/
|
||||
if (frame->type == SSH_FRAME_TYPE_DATA_NSQ)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Check if SEQ has been seen recently (i.e. packet was
|
||||
* re-transmitted and we should ignore it).
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(ptl->rx.blocked.seqs); i++) {
|
||||
if (likely(ptl->rx.blocked.seqs[i] != seq))
|
||||
if (likely(ptl->rx.blocked.seqs[i] != frame->seq))
|
||||
continue;
|
||||
|
||||
ptl_dbg(ptl, "ptl: ignoring repeated data packet\n");
|
||||
@@ -1613,7 +1629,7 @@ static bool ssh_ptl_rx_retransmit_check(struct ssh_ptl *ptl, u8 seq)
|
||||
}
|
||||
|
||||
/* Update list of blocked sequence IDs. */
|
||||
ptl->rx.blocked.seqs[ptl->rx.blocked.offset] = seq;
|
||||
ptl->rx.blocked.seqs[ptl->rx.blocked.offset] = frame->seq;
|
||||
ptl->rx.blocked.offset = (ptl->rx.blocked.offset + 1)
|
||||
% ARRAY_SIZE(ptl->rx.blocked.seqs);
|
||||
|
||||
@@ -1624,7 +1640,7 @@ static void ssh_ptl_rx_dataframe(struct ssh_ptl *ptl,
|
||||
const struct ssh_frame *frame,
|
||||
const struct ssam_span *payload)
|
||||
{
|
||||
if (ssh_ptl_rx_retransmit_check(ptl, frame->seq))
|
||||
if (ssh_ptl_rx_retransmit_check(ptl, frame))
|
||||
return;
|
||||
|
||||
ptl->ops.data_received(ptl, payload);
|
||||
|
||||
@@ -18,6 +18,8 @@
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
|
||||
#include <xen/xen.h>
|
||||
|
||||
static void intel_pmc_core_release(struct device *dev)
|
||||
{
|
||||
kfree(dev);
|
||||
@@ -53,6 +55,13 @@ static int __init pmc_core_platform_init(void)
|
||||
if (acpi_dev_present("INT33A1", NULL, -1))
|
||||
return -ENODEV;
|
||||
|
||||
/*
|
||||
* Skip forcefully attaching the device for VMs. Make an exception for
|
||||
* Xen dom0, which does have full hardware access.
|
||||
*/
|
||||
if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR) && !xen_initial_domain())
|
||||
return -ENODEV;
|
||||
|
||||
if (!x86_match_cpu(intel_pmc_core_platform_ids))
|
||||
return -ENODEV;
|
||||
|
||||
|
||||
@@ -884,7 +884,7 @@ static int zfcp_fsf_req_send(struct zfcp_fsf_req *req)
|
||||
const bool is_srb = zfcp_fsf_req_is_status_read_buffer(req);
|
||||
struct zfcp_adapter *adapter = req->adapter;
|
||||
struct zfcp_qdio *qdio = adapter->qdio;
|
||||
int req_id = req->req_id;
|
||||
unsigned long req_id = req->req_id;
|
||||
|
||||
zfcp_reqlist_add(adapter->req_list, req);
|
||||
|
||||
|
||||
@@ -7211,8 +7211,12 @@ static int sdebug_add_host_helper(int per_host_idx)
|
||||
dev_set_name(&sdbg_host->dev, "adapter%d", sdebug_num_hosts);
|
||||
|
||||
error = device_register(&sdbg_host->dev);
|
||||
if (error)
|
||||
if (error) {
|
||||
spin_lock(&sdebug_host_list_lock);
|
||||
list_del(&sdbg_host->host_list);
|
||||
spin_unlock(&sdebug_host_list_lock);
|
||||
goto clean;
|
||||
}
|
||||
|
||||
++sdebug_num_hosts;
|
||||
return 0;
|
||||
|
||||
@@ -716,12 +716,17 @@ int sas_phy_add(struct sas_phy *phy)
|
||||
int error;
|
||||
|
||||
error = device_add(&phy->dev);
|
||||
if (!error) {
|
||||
transport_add_device(&phy->dev);
|
||||
transport_configure_device(&phy->dev);
|
||||
}
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
return error;
|
||||
error = transport_add_device(&phy->dev);
|
||||
if (error) {
|
||||
device_del(&phy->dev);
|
||||
return error;
|
||||
}
|
||||
transport_configure_device(&phy->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(sas_phy_add);
|
||||
|
||||
|
||||
@@ -839,6 +839,8 @@ static struct siox_device *siox_device_add(struct siox_master *smaster,
|
||||
|
||||
err_device_register:
|
||||
/* don't care to make the buffer smaller again */
|
||||
put_device(&sdevice->dev);
|
||||
sdevice = NULL;
|
||||
|
||||
err_buf_alloc:
|
||||
siox_master_unlock(smaster);
|
||||
|
||||
@@ -23,7 +23,7 @@ config SLIM_QCOM_CTRL
|
||||
config SLIM_QCOM_NGD_CTRL
|
||||
tristate "Qualcomm SLIMbus Satellite Non-Generic Device Component"
|
||||
depends on HAS_IOMEM && DMA_ENGINE && NET
|
||||
depends on QCOM_RPROC_COMMON || COMPILE_TEST
|
||||
depends on QCOM_RPROC_COMMON || (COMPILE_TEST && !QCOM_RPROC_COMMON)
|
||||
depends on ARCH_QCOM || COMPILE_TEST
|
||||
select QCOM_QMI_HELPERS
|
||||
select QCOM_PDR_HELPERS
|
||||
|
||||
@@ -67,10 +67,10 @@ static const int slim_presence_rate_table[] = {
|
||||
384000,
|
||||
768000,
|
||||
0, /* Reserved */
|
||||
110250,
|
||||
220500,
|
||||
441000,
|
||||
882000,
|
||||
11025,
|
||||
22050,
|
||||
44100,
|
||||
88200,
|
||||
176400,
|
||||
352800,
|
||||
705600,
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#define REV_B1 0x21
|
||||
|
||||
@@ -56,6 +57,7 @@ static u32 __init imx8mq_soc_revision(void)
|
||||
void __iomem *ocotp_base;
|
||||
u32 magic;
|
||||
u32 rev;
|
||||
struct clk *clk;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
|
||||
if (!np)
|
||||
@@ -63,6 +65,13 @@ static u32 __init imx8mq_soc_revision(void)
|
||||
|
||||
ocotp_base = of_iomap(np, 0);
|
||||
WARN_ON(!ocotp_base);
|
||||
clk = of_clk_get_by_name(np, NULL);
|
||||
if (!clk) {
|
||||
WARN_ON(!clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
/*
|
||||
* SOC revision on older imx8mq is not available in fuses so query
|
||||
@@ -79,6 +88,8 @@ static u32 __init imx8mq_soc_revision(void)
|
||||
soc_uid <<= 32;
|
||||
soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
|
||||
|
||||
clk_disable_unprepare(clk);
|
||||
clk_put(clk);
|
||||
iounmap(ocotp_base);
|
||||
of_node_put(np);
|
||||
|
||||
|
||||
@@ -886,6 +886,7 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
|
||||
static DEFINE_RATELIMIT_STATE(rs,
|
||||
DEFAULT_RATELIMIT_INTERVAL * 10,
|
||||
1);
|
||||
ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
|
||||
if (__ratelimit(&rs))
|
||||
dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
|
||||
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
|
||||
|
||||
@@ -397,6 +397,7 @@ static int tcm_loop_setup_hba_bus(struct tcm_loop_hba *tl_hba, int tcm_loop_host
|
||||
ret = device_register(&tl_hba->dev);
|
||||
if (ret) {
|
||||
pr_err("device_register() failed for tl_hba->dev: %d\n", ret);
|
||||
put_device(&tl_hba->dev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
@@ -1073,7 +1074,7 @@ check_len:
|
||||
*/
|
||||
ret = tcm_loop_setup_hba_bus(tl_hba, tcm_loop_hba_no_cnt);
|
||||
if (ret)
|
||||
goto out;
|
||||
return ERR_PTR(ret);
|
||||
|
||||
sh = tl_hba->sh;
|
||||
tcm_loop_hba_no_cnt++;
|
||||
|
||||
@@ -1577,7 +1577,7 @@ static struct gsm_control *gsm_control_send(struct gsm_mux *gsm,
|
||||
unsigned int command, u8 *data, int clen)
|
||||
{
|
||||
struct gsm_control *ctrl = kzalloc(sizeof(struct gsm_control),
|
||||
GFP_KERNEL);
|
||||
GFP_ATOMIC);
|
||||
unsigned long flags;
|
||||
if (ctrl == NULL)
|
||||
return NULL;
|
||||
|
||||
@@ -177,6 +177,9 @@ static int ehl_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
|
||||
* matching with the registered General Purpose DMA controllers.
|
||||
*/
|
||||
up->dma = dma;
|
||||
|
||||
lpss->dma_maxburst = 16;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -278,8 +281,13 @@ static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port
|
||||
struct dw_dma_slave *rx_param, *tx_param;
|
||||
struct device *dev = port->port.dev;
|
||||
|
||||
if (!lpss->dma_param.dma_dev)
|
||||
if (!lpss->dma_param.dma_dev) {
|
||||
dma = port->dma;
|
||||
if (dma)
|
||||
goto out_configuration_only;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
|
||||
if (!rx_param)
|
||||
@@ -290,16 +298,18 @@ static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port
|
||||
return -ENOMEM;
|
||||
|
||||
*rx_param = lpss->dma_param;
|
||||
dma->rxconf.src_maxburst = lpss->dma_maxburst;
|
||||
|
||||
*tx_param = lpss->dma_param;
|
||||
dma->txconf.dst_maxburst = lpss->dma_maxburst;
|
||||
|
||||
dma->fn = lpss8250_dma_filter;
|
||||
dma->rx_param = rx_param;
|
||||
dma->tx_param = tx_param;
|
||||
|
||||
port->dma = dma;
|
||||
|
||||
out_configuration_only:
|
||||
dma->rxconf.src_maxburst = lpss->dma_maxburst;
|
||||
dma->txconf.dst_maxburst = lpss->dma_maxburst;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -157,7 +157,11 @@ static u32 uart_read(struct uart_8250_port *up, u32 reg)
|
||||
return readl(up->port.membase + (reg << up->port.regshift));
|
||||
}
|
||||
|
||||
static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
/*
|
||||
* Called on runtime PM resume path from omap8250_restore_regs(), and
|
||||
* omap8250_set_mctrl().
|
||||
*/
|
||||
static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
{
|
||||
struct uart_8250_port *up = up_to_u8250p(port);
|
||||
struct omap8250_priv *priv = up->port.private_data;
|
||||
@@ -181,6 +185,20 @@ static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
}
|
||||
}
|
||||
|
||||
static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = pm_runtime_resume_and_get(port->dev);
|
||||
if (err)
|
||||
return;
|
||||
|
||||
__omap8250_set_mctrl(port, mctrl);
|
||||
|
||||
pm_runtime_mark_last_busy(port->dev);
|
||||
pm_runtime_put_autosuspend(port->dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
|
||||
* The access to uart register after MDR1 Access
|
||||
@@ -193,27 +211,10 @@ static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
|
||||
struct omap8250_priv *priv)
|
||||
{
|
||||
u8 timeout = 255;
|
||||
|
||||
serial_out(up, UART_OMAP_MDR1, priv->mdr1);
|
||||
udelay(2);
|
||||
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
|
||||
UART_FCR_CLEAR_RCVR);
|
||||
/*
|
||||
* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
|
||||
* TX_FIFO_E bit is 1.
|
||||
*/
|
||||
while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
|
||||
(UART_LSR_THRE | UART_LSR_DR))) {
|
||||
timeout--;
|
||||
if (!timeout) {
|
||||
/* Should *never* happen. we warn and carry on */
|
||||
dev_crit(up->port.dev, "Errata i202: timedout %x\n",
|
||||
serial_in(up, UART_LSR));
|
||||
break;
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
|
||||
@@ -341,7 +342,7 @@ static void omap8250_restore_regs(struct uart_8250_port *up)
|
||||
|
||||
omap8250_update_mdr1(up, priv);
|
||||
|
||||
up->port.ops->set_mctrl(&up->port, up->port.mctrl);
|
||||
__omap8250_set_mctrl(&up->port, up->port.mctrl);
|
||||
|
||||
if (up->port.rs485.flags & SER_RS485_ENABLED)
|
||||
serial8250_em485_stop_tx(up);
|
||||
@@ -1474,9 +1475,15 @@ err:
|
||||
static int omap8250_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct omap8250_priv *priv = platform_get_drvdata(pdev);
|
||||
int err;
|
||||
|
||||
err = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
flush_work(&priv->qos_work);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
serial8250_unregister_port(priv->line);
|
||||
cpu_latency_qos_remove_request(&priv->pm_qos_request);
|
||||
|
||||
@@ -1885,10 +1885,13 @@ EXPORT_SYMBOL_GPL(serial8250_modem_status);
|
||||
static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
|
||||
{
|
||||
switch (iir & 0x3f) {
|
||||
case UART_IIR_RX_TIMEOUT:
|
||||
serial8250_rx_dma_flush(up);
|
||||
case UART_IIR_RDI:
|
||||
if (!up->dma->rx_running)
|
||||
break;
|
||||
fallthrough;
|
||||
case UART_IIR_RLSI:
|
||||
case UART_IIR_RX_TIMEOUT:
|
||||
serial8250_rx_dma_flush(up);
|
||||
return true;
|
||||
}
|
||||
return up->dma->rx_dma(up);
|
||||
|
||||
@@ -2563,6 +2563,7 @@ static const struct dev_pm_ops imx_uart_pm_ops = {
|
||||
.suspend_noirq = imx_uart_suspend_noirq,
|
||||
.resume_noirq = imx_uart_resume_noirq,
|
||||
.freeze_noirq = imx_uart_suspend_noirq,
|
||||
.thaw_noirq = imx_uart_resume_noirq,
|
||||
.restore_noirq = imx_uart_resume_noirq,
|
||||
.suspend = imx_uart_suspend,
|
||||
.resume = imx_uart_resume,
|
||||
|
||||
@@ -23,11 +23,37 @@
|
||||
#define CFG_RXDET_P3_EN BIT(15)
|
||||
#define LPM_2_STB_SWITCH_EN BIT(25)
|
||||
|
||||
static int xhci_cdns3_suspend_quirk(struct usb_hcd *hcd);
|
||||
static void xhci_cdns3_plat_start(struct usb_hcd *hcd)
|
||||
{
|
||||
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
||||
u32 value;
|
||||
|
||||
/* set usbcmd.EU3S */
|
||||
value = readl(&xhci->op_regs->command);
|
||||
value |= CMD_PM_INDEX;
|
||||
writel(value, &xhci->op_regs->command);
|
||||
|
||||
if (hcd->regs) {
|
||||
value = readl(hcd->regs + XECP_AUX_CTRL_REG1);
|
||||
value |= CFG_RXDET_P3_EN;
|
||||
writel(value, hcd->regs + XECP_AUX_CTRL_REG1);
|
||||
|
||||
value = readl(hcd->regs + XECP_PORT_CAP_REG);
|
||||
value |= LPM_2_STB_SWITCH_EN;
|
||||
writel(value, hcd->regs + XECP_PORT_CAP_REG);
|
||||
}
|
||||
}
|
||||
|
||||
static int xhci_cdns3_resume_quirk(struct usb_hcd *hcd)
|
||||
{
|
||||
xhci_cdns3_plat_start(hcd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct xhci_plat_priv xhci_plat_cdns3_xhci = {
|
||||
.quirks = XHCI_SKIP_PHY_INIT | XHCI_AVOID_BEI,
|
||||
.suspend_quirk = xhci_cdns3_suspend_quirk,
|
||||
.plat_start = xhci_cdns3_plat_start,
|
||||
.resume_quirk = xhci_cdns3_resume_quirk,
|
||||
};
|
||||
|
||||
static int __cdns_host_init(struct cdns *cdns)
|
||||
@@ -89,32 +115,6 @@ err1:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int xhci_cdns3_suspend_quirk(struct usb_hcd *hcd)
|
||||
{
|
||||
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
||||
u32 value;
|
||||
|
||||
if (pm_runtime_status_suspended(hcd->self.controller))
|
||||
return 0;
|
||||
|
||||
/* set usbcmd.EU3S */
|
||||
value = readl(&xhci->op_regs->command);
|
||||
value |= CMD_PM_INDEX;
|
||||
writel(value, &xhci->op_regs->command);
|
||||
|
||||
if (hcd->regs) {
|
||||
value = readl(hcd->regs + XECP_AUX_CTRL_REG1);
|
||||
value |= CFG_RXDET_P3_EN;
|
||||
writel(value, hcd->regs + XECP_AUX_CTRL_REG1);
|
||||
|
||||
value = readl(hcd->regs + XECP_PORT_CAP_REG);
|
||||
value |= LPM_2_STB_SWITCH_EN;
|
||||
writel(value, hcd->regs + XECP_PORT_CAP_REG);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cdns_host_exit(struct cdns *cdns)
|
||||
{
|
||||
kfree(cdns->xhci_plat_data);
|
||||
|
||||
@@ -256,8 +256,10 @@ static void ci_otg_del_timer(struct ci_hdrc *ci, enum otg_fsm_timer t)
|
||||
ci->enabled_otg_timer_bits &= ~(1 << t);
|
||||
if (ci->next_otg_timer == t) {
|
||||
if (ci->enabled_otg_timer_bits == 0) {
|
||||
spin_unlock_irqrestore(&ci->lock, flags);
|
||||
/* No enabled timers after delete it */
|
||||
hrtimer_cancel(&ci->otg_fsm_hrtimer);
|
||||
spin_lock_irqsave(&ci->lock, flags);
|
||||
ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
|
||||
} else {
|
||||
/* Find the next timer */
|
||||
|
||||
@@ -362,6 +362,9 @@ static const struct usb_device_id usb_quirk_list[] = {
|
||||
{ USB_DEVICE(0x0781, 0x5583), .driver_info = USB_QUIRK_NO_LPM },
|
||||
{ USB_DEVICE(0x0781, 0x5591), .driver_info = USB_QUIRK_NO_LPM },
|
||||
|
||||
/* Realforce 87U Keyboard */
|
||||
{ USB_DEVICE(0x0853, 0x011b), .driver_info = USB_QUIRK_NO_LPM },
|
||||
|
||||
/* M-Systems Flash Disk Pioneers */
|
||||
{ USB_DEVICE(0x08ec, 0x1000), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
|
||||
|
||||
@@ -10,13 +10,8 @@
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "../host/xhci-plat.h"
|
||||
#include "core.h"
|
||||
|
||||
static const struct xhci_plat_priv dwc3_xhci_plat_priv = {
|
||||
.quirks = XHCI_SKIP_PHY_INIT,
|
||||
};
|
||||
|
||||
static int dwc3_host_get_irq(struct dwc3 *dwc)
|
||||
{
|
||||
struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
|
||||
@@ -92,11 +87,6 @@ int dwc3_host_init(struct dwc3 *dwc)
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = platform_device_add_data(xhci, &dwc3_xhci_plat_priv,
|
||||
sizeof(dwc3_xhci_plat_priv));
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
|
||||
|
||||
if (dwc->usb3_lpm_capable)
|
||||
|
||||
@@ -285,7 +285,7 @@ static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val)
|
||||
{
|
||||
struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
|
||||
|
||||
if (IS_ERR_OR_NULL(usb_dev->gpio_desc))
|
||||
if (!usb_dev->gpio_desc)
|
||||
return;
|
||||
|
||||
gpiod_set_value(usb_dev->gpio_desc, val);
|
||||
@@ -406,9 +406,11 @@ static int bcma_hcd_probe(struct bcma_device *core)
|
||||
return -ENOMEM;
|
||||
usb_dev->core = core;
|
||||
|
||||
if (core->dev.of_node)
|
||||
usb_dev->gpio_desc = devm_gpiod_get(&core->dev, "vcc",
|
||||
GPIOD_OUT_HIGH);
|
||||
usb_dev->gpio_desc = devm_gpiod_get_optional(&core->dev, "vcc",
|
||||
GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(usb_dev->gpio_desc))
|
||||
return dev_err_probe(&core->dev, PTR_ERR(usb_dev->gpio_desc),
|
||||
"error obtaining VCC GPIO");
|
||||
|
||||
switch (core->id.id) {
|
||||
case BCMA_CORE_USB20_HOST:
|
||||
|
||||
@@ -162,6 +162,8 @@ static void option_instat_callback(struct urb *urb);
|
||||
#define NOVATELWIRELESS_PRODUCT_G2 0xA010
|
||||
#define NOVATELWIRELESS_PRODUCT_MC551 0xB001
|
||||
|
||||
#define UBLOX_VENDOR_ID 0x1546
|
||||
|
||||
/* AMOI PRODUCTS */
|
||||
#define AMOI_VENDOR_ID 0x1614
|
||||
#define AMOI_PRODUCT_H01 0x0800
|
||||
@@ -240,7 +242,6 @@ static void option_instat_callback(struct urb *urb);
|
||||
#define QUECTEL_PRODUCT_UC15 0x9090
|
||||
/* These u-blox products use Qualcomm's vendor ID */
|
||||
#define UBLOX_PRODUCT_R410M 0x90b2
|
||||
#define UBLOX_PRODUCT_R6XX 0x90fa
|
||||
/* These Yuga products use Qualcomm's vendor ID */
|
||||
#define YUGA_PRODUCT_CLM920_NC5 0x9625
|
||||
|
||||
@@ -581,6 +582,9 @@ static void option_instat_callback(struct urb *urb);
|
||||
#define OPPO_VENDOR_ID 0x22d9
|
||||
#define OPPO_PRODUCT_R11 0x276c
|
||||
|
||||
/* Sierra Wireless products */
|
||||
#define SIERRA_VENDOR_ID 0x1199
|
||||
#define SIERRA_PRODUCT_EM9191 0x90d3
|
||||
|
||||
/* Device flags */
|
||||
|
||||
@@ -1124,8 +1128,16 @@ static const struct usb_device_id option_ids[] = {
|
||||
/* u-blox products using Qualcomm vendor ID */
|
||||
{ USB_DEVICE(QUALCOMM_VENDOR_ID, UBLOX_PRODUCT_R410M),
|
||||
.driver_info = RSVD(1) | RSVD(3) },
|
||||
{ USB_DEVICE(QUALCOMM_VENDOR_ID, UBLOX_PRODUCT_R6XX),
|
||||
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x908b), /* u-blox LARA-R6 00B */
|
||||
.driver_info = RSVD(4) },
|
||||
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x90fa),
|
||||
.driver_info = RSVD(3) },
|
||||
/* u-blox products */
|
||||
{ USB_DEVICE(UBLOX_VENDOR_ID, 0x1341) }, /* u-blox LARA-L6 */
|
||||
{ USB_DEVICE(UBLOX_VENDOR_ID, 0x1342), /* u-blox LARA-L6 (RMNET) */
|
||||
.driver_info = RSVD(4) },
|
||||
{ USB_DEVICE(UBLOX_VENDOR_ID, 0x1343), /* u-blox LARA-L6 (ECM) */
|
||||
.driver_info = RSVD(4) },
|
||||
/* Quectel products using Quectel vendor ID */
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC21, 0xff, 0xff, 0xff),
|
||||
.driver_info = NUMEP2 },
|
||||
@@ -2167,6 +2179,7 @@ static const struct usb_device_id option_ids[] = {
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x010a, 0xff) }, /* Fibocom MA510 (ECM mode) */
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(0x2cb7, 0x010b, 0xff, 0xff, 0x30) }, /* Fibocom FG150 Diag */
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(0x2cb7, 0x010b, 0xff, 0, 0) }, /* Fibocom FG150 AT */
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x0111, 0xff) }, /* Fibocom FM160 (MBIM mode) */
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a0, 0xff) }, /* Fibocom NL668-AM/NL652-EU (laptop MBIM) */
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a2, 0xff) }, /* Fibocom FM101-GL (laptop MBIM) */
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a4, 0xff), /* Fibocom FM101-GL (laptop MBIM) */
|
||||
@@ -2176,6 +2189,8 @@ static const struct usb_device_id option_ids[] = {
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1405, 0xff) }, /* GosunCn GM500 MBIM */
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) }, /* GosunCn GM500 ECM/NCM */
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) },
|
||||
{ } /* Terminating entry */
|
||||
};
|
||||
MODULE_DEVICE_TABLE(usb, option_ids);
|
||||
|
||||
@@ -352,13 +352,24 @@ pmc_usb_mux_usb4(struct pmc_usb_port *port, struct typec_mux_state *state)
|
||||
return pmc_usb_command(port, (void *)&req, sizeof(req));
|
||||
}
|
||||
|
||||
static int pmc_usb_mux_safe_state(struct pmc_usb_port *port)
|
||||
static int pmc_usb_mux_safe_state(struct pmc_usb_port *port,
|
||||
struct typec_mux_state *state)
|
||||
{
|
||||
u8 msg;
|
||||
|
||||
if (IOM_PORT_ACTIVITY_IS(port->iom_status, SAFE_MODE))
|
||||
return 0;
|
||||
|
||||
if ((IOM_PORT_ACTIVITY_IS(port->iom_status, DP) ||
|
||||
IOM_PORT_ACTIVITY_IS(port->iom_status, DP_MFD)) &&
|
||||
state->alt && state->alt->svid == USB_TYPEC_DP_SID)
|
||||
return 0;
|
||||
|
||||
if ((IOM_PORT_ACTIVITY_IS(port->iom_status, TBT) ||
|
||||
IOM_PORT_ACTIVITY_IS(port->iom_status, ALT_MODE_TBT_USB)) &&
|
||||
state->alt && state->alt->svid == USB_TYPEC_TBT_SID)
|
||||
return 0;
|
||||
|
||||
msg = PMC_USB_SAFE_MODE;
|
||||
msg |= port->usb3_port << PMC_USB_MSG_USB3_PORT_SHIFT;
|
||||
|
||||
@@ -426,7 +437,7 @@ pmc_usb_mux_set(struct typec_mux *mux, struct typec_mux_state *state)
|
||||
return 0;
|
||||
|
||||
if (state->mode == TYPEC_STATE_SAFE)
|
||||
return pmc_usb_mux_safe_state(port);
|
||||
return pmc_usb_mux_safe_state(port, state);
|
||||
if (state->mode == TYPEC_STATE_USB)
|
||||
return pmc_usb_connect(port, port->role);
|
||||
|
||||
|
||||
@@ -228,7 +228,7 @@ static int register_pcpu(struct pcpu *pcpu)
|
||||
|
||||
err = device_register(dev);
|
||||
if (err) {
|
||||
pcpu_release(dev);
|
||||
put_device(dev);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user